diff -Nrcpad gcc-13-20250814/LAST_UPDATED gcc-13-20250821/LAST_UPDATED
*** gcc-13-20250814/LAST_UPDATED	Thu Aug 14 22:33:04 2025
--- gcc-13-20250821/LAST_UPDATED	Thu Aug 21 22:33:45 2025
***************
*** 1 ****
! Obtained from git: releases/gcc-13 revision 1c6880c740c478980a8e09325ec7c5939a7f0a09
--- 1 ----
! Obtained from git: releases/gcc-13 revision 9d4a69518ef8665d36265893f9ca26d232eb439d
diff -Nrcpad gcc-13-20250814/MD5SUMS gcc-13-20250821/MD5SUMS
*** gcc-13-20250814/MD5SUMS	Thu Aug 14 22:33:12 2025
--- gcc-13-20250821/MD5SUMS	Thu Aug 21 22:34:09 2025
***************
*** 1,5 ****
  # This file contains the MD5 checksums of the files in the
! # gcc-13-20250814.tar.xz tarball.
  #
  # Besides verifying that all files in the tarball were correctly expanded,
  # it also can be used to determine if any files have changed since the
--- 1,5 ----
  # This file contains the MD5 checksums of the files in the
! # gcc-13-20250821.tar.xz tarball.
  #
  # Besides verifying that all files in the tarball were correctly expanded,
  # it also can be used to determine if any files have changed since the
*************** d32239bcb673463ab874e80d47fae504  COPYIN
*** 21,27 ****
  fd4ecdf5d672efe2b0e409aca9cf9446  ChangeLog.jit
  09538b708302f1735f6fa05b622ecf5e  ChangeLog.tree-ssa
  24ab760126489e69436a43185dc3d202  INSTALL/README
! 446f9cd2b189527e3e3ec4a7dd17c1d7  LAST_UPDATED
  81b3330d422f3ce1ef8b720dfae35068  MAINTAINERS
  2b61ddbd876fa839639a7ca551773426  Makefile.def
  5d2d6a74f897f8158d37f5f2ec6877ce  Makefile.in
--- 21,27 ----
  fd4ecdf5d672efe2b0e409aca9cf9446  ChangeLog.jit
  09538b708302f1735f6fa05b622ecf5e  ChangeLog.tree-ssa
  24ab760126489e69436a43185dc3d202  INSTALL/README
! 79593440a612e61b0c866e90a78e430c  LAST_UPDATED
  81b3330d422f3ce1ef8b720dfae35068  MAINTAINERS
  2b61ddbd876fa839639a7ca551773426  Makefile.def
  5d2d6a74f897f8158d37f5f2ec6877ce  Makefile.in
*************** a22e70b3f29292d0e628450f4bb11e62  fixinc
*** 475,481 ****
  a916467b91076e631dd8edb7424769c7  gcc/COPYING.LIB
  d32239bcb673463ab874e80d47fae504  gcc/COPYING3
  6a6a8e020838b23406c81b19c1d46df6  gcc/COPYING3.LIB
! 8fab9c20f672ff347ec09bbb2c346c7d  gcc/ChangeLog
  a3b63c675afa7a655cc2bfa8a907af79  gcc/ChangeLog-1997
  d9a88529352a010253c2e8fb1ed6023b  gcc/ChangeLog-1998
  240f08f81cb4699e8b49347db38233db  gcc/ChangeLog-1999
--- 475,481 ----
  a916467b91076e631dd8edb7424769c7  gcc/COPYING.LIB
  d32239bcb673463ab874e80d47fae504  gcc/COPYING3
  6a6a8e020838b23406c81b19c1d46df6  gcc/COPYING3.LIB
! 8591268fb408106f8b7766027874188a  gcc/ChangeLog
  a3b63c675afa7a655cc2bfa8a907af79  gcc/ChangeLog-1997
  d9a88529352a010253c2e8fb1ed6023b  gcc/ChangeLog-1998
  240f08f81cb4699e8b49347db38233db  gcc/ChangeLog-1999
*************** fb3fadb88e1d2b3b640cfaaa5ff11780  gcc/Ch
*** 510,516 ****
  3eb07e0b2e542409bf73d359f7f65609  gcc/ChangeLog.ptr
  e13638e26743ba41e6011b76cc00d9a9  gcc/ChangeLog.tree-ssa
  739ab47f6425bcea1d05e4fc0542de54  gcc/ChangeLog.tuples
! c9f8ec33503c7f170ac73774182540e7  gcc/DATESTAMP
  d41d8cd98f00b204e9800998ecf8427e  gcc/DEV-PHASE
  eb92e1ff5e982ca07e173e0eb286d243  gcc/FSFChangeLog
  30e1e33411566388b3164558482dc5e6  gcc/FSFChangeLog.10
--- 510,516 ----
  3eb07e0b2e542409bf73d359f7f65609  gcc/ChangeLog.ptr
  e13638e26743ba41e6011b76cc00d9a9  gcc/ChangeLog.tree-ssa
  739ab47f6425bcea1d05e4fc0542de54  gcc/ChangeLog.tuples
! c539ece43b62061b2c13536d7877052d  gcc/DATESTAMP
  d41d8cd98f00b204e9800998ecf8427e  gcc/DEV-PHASE
  eb92e1ff5e982ca07e173e0eb286d243  gcc/FSFChangeLog
  30e1e33411566388b3164558482dc5e6  gcc/FSFChangeLog.10
*************** fb2af51188d71aa0ad4edbb97be3fe41  gcc/co
*** 3295,3306 ****
  45d75fc8775a4aa44d49b8571fdf7b29  gcc/config/aarch64/aarch64-sve-builtins.cc
  d944ba1876e827e8299a96fc31433c22  gcc/config/aarch64/aarch64-sve-builtins.def
  4ec15579b7cd3388c4d8eb7117540e35  gcc/config/aarch64/aarch64-sve-builtins.h
! 8527b14f19d829b3e608d7a35b7f216c  gcc/config/aarch64/aarch64-sve.md
  539c5094467274e03fa1ea0087d02d65  gcc/config/aarch64/aarch64-sve2.md
  7110ab6fb22b0e5dc8f7c105640b73f4  gcc/config/aarch64/aarch64-tune.md
  59a2e50c10aa66ea9757d8594c3cb6dc  gcc/config/aarch64/aarch64-tuning-flags.def
  703c876523c318a07e43cdfe4a0a2bee  gcc/config/aarch64/aarch64-vxworks.h
! e3d60529c154e5cee18711ff9142b61d  gcc/config/aarch64/aarch64.cc
  8df0eba1e11a7d9dcc4820353ddc6ba5  gcc/config/aarch64/aarch64.h
  9a34b88782e645b1f51ad5bf799a9ce5  gcc/config/aarch64/aarch64.md
  27b3d58e07a631b044b51b2920e36271  gcc/config/aarch64/aarch64.opt
--- 3295,3306 ----
  45d75fc8775a4aa44d49b8571fdf7b29  gcc/config/aarch64/aarch64-sve-builtins.cc
  d944ba1876e827e8299a96fc31433c22  gcc/config/aarch64/aarch64-sve-builtins.def
  4ec15579b7cd3388c4d8eb7117540e35  gcc/config/aarch64/aarch64-sve-builtins.h
! 9a44af0b55f9dc930d1ba4d89dc3eeb1  gcc/config/aarch64/aarch64-sve.md
  539c5094467274e03fa1ea0087d02d65  gcc/config/aarch64/aarch64-sve2.md
  7110ab6fb22b0e5dc8f7c105640b73f4  gcc/config/aarch64/aarch64-tune.md
  59a2e50c10aa66ea9757d8594c3cb6dc  gcc/config/aarch64/aarch64-tuning-flags.def
  703c876523c318a07e43cdfe4a0a2bee  gcc/config/aarch64/aarch64-vxworks.h
! df041521ccd5d43ee927ad2edf1204ed  gcc/config/aarch64/aarch64.cc
  8df0eba1e11a7d9dcc4820353ddc6ba5  gcc/config/aarch64/aarch64.h
  9a34b88782e645b1f51ad5bf799a9ce5  gcc/config/aarch64/aarch64.md
  27b3d58e07a631b044b51b2920e36271  gcc/config/aarch64/aarch64.opt
*************** f0880103f5af621d5051b6b0ef710ba1  gcc/co
*** 3554,3560 ****
  bcef8a3e0aed8ec9bca46e7c98959588  gcc/config/avr/gen-avr-mmcu-texi.cc
  b66a49b68d591a6c0b7af5fc6a368c25  gcc/config/avr/genmultilib.awk
  bcf32309fb3db2a9d7062f64b15abd3a  gcc/config/avr/predicates.md
! 55f61938445efff9a372e6135a536342  gcc/config/avr/specs.h
  a90b049a5422ac5aa92130f8d01d1a39  gcc/config/avr/stdfix.h
  5f9b9e751722dbcab353617d7f7521a1  gcc/config/avr/t-avr
  17266d6ea4ed538b3d9b230711b7213f  gcc/config/bfin/bfin-modes.def
--- 3554,3560 ----
  bcef8a3e0aed8ec9bca46e7c98959588  gcc/config/avr/gen-avr-mmcu-texi.cc
  b66a49b68d591a6c0b7af5fc6a368c25  gcc/config/avr/genmultilib.awk
  bcf32309fb3db2a9d7062f64b15abd3a  gcc/config/avr/predicates.md
! 54e187fda60b9580910b0954e5506955  gcc/config/avr/specs.h
  a90b049a5422ac5aa92130f8d01d1a39  gcc/config/avr/stdfix.h
  5f9b9e751722dbcab353617d7f7521a1  gcc/config/avr/t-avr
  17266d6ea4ed538b3d9b230711b7213f  gcc/config/bfin/bfin-modes.def
*************** bae9bee7bfae062bb68f7c3b8d6acdb0  gcc/fo
*** 5683,5689 ****
  9d3f4e62a09a4f1b7e01c2611985469b  gcc/function-tests.cc
  dc0db54f4e74be29d19799f88ed3a0f9  gcc/function.cc
  26caa4b20f75c2eb576da5bea538a2bc  gcc/function.h
! 97522e4b206b460428df4f324aa88fe4  gcc/fwprop.cc
  8b44f92603525757cdb88056f5f18ca2  gcc/gcc-ar.cc
  5d0b85771982e816a798a8206c3fc74c  gcc/gcc-main.cc
  73e2fac76430bce31ea211c315bda445  gcc/gcc-plugin.h
--- 5683,5689 ----
  9d3f4e62a09a4f1b7e01c2611985469b  gcc/function-tests.cc
  dc0db54f4e74be29d19799f88ed3a0f9  gcc/function.cc
  26caa4b20f75c2eb576da5bea538a2bc  gcc/function.h
! f2f74988d8e8927907da6f1d3f3d09ca  gcc/fwprop.cc
  8b44f92603525757cdb88056f5f18ca2  gcc/gcc-ar.cc
  5d0b85771982e816a798a8206c3fc74c  gcc/gcc-main.cc
  73e2fac76430bce31ea211c315bda445  gcc/gcc-plugin.h
*************** b829ed0032c899e107be2db349c913f3  gcc/ta
*** 7637,7643 ****
  811da275a2b9d3186a6decf96c01b0ed  gcc/targhooks.cc
  edb193a32070c4a7626fb75382def9b9  gcc/targhooks.h
  f39fcaa8197187283ccfed40107b426d  gcc/testsuite/.gitattributes
! 5b5d9f2df40e7b6754773d579cf728f0  gcc/testsuite/ChangeLog
  862f04afbd87da2cc6bc432c3f28430f  gcc/testsuite/ChangeLog-1993-2007
  029a5d8dacd25eb5d4711452ac448e5b  gcc/testsuite/ChangeLog-2008
  13ac28c41d51b66b4ec40dba6bd50f39  gcc/testsuite/ChangeLog-2009
--- 7637,7643 ----
  811da275a2b9d3186a6decf96c01b0ed  gcc/targhooks.cc
  edb193a32070c4a7626fb75382def9b9  gcc/targhooks.h
  f39fcaa8197187283ccfed40107b426d  gcc/testsuite/.gitattributes
! eb58cc809b9f658e40dfd7bb0e399ccd  gcc/testsuite/ChangeLog
  862f04afbd87da2cc6bc432c3f28430f  gcc/testsuite/ChangeLog-1993-2007
  029a5d8dacd25eb5d4711452ac448e5b  gcc/testsuite/ChangeLog-2008
  13ac28c41d51b66b4ec40dba6bd50f39  gcc/testsuite/ChangeLog-2009
*************** ab6c5e333d0a740ae5ecff69966813a2  gcc/te
*** 32856,32861 ****
--- 32856,32862 ----
  0dc60096927b240a4fb696311ad6b402  gcc/testsuite/g++.target/aarch64/sve/pr107920.C
  a36c6629cdaa92f5a41aa0c862cf5a54  gcc/testsuite/g++.target/aarch64/sve/pr119610-sve.C
  a99137b765de9aa71ce57dc37592e682  gcc/testsuite/g++.target/aarch64/sve/pr119706.C
+ 81119ead1d39599a647b5c79f9d21a85  gcc/testsuite/g++.target/aarch64/sve/pr121449.C
  29fcc7f7695fcab2e4779698100f3053  gcc/testsuite/g++.target/aarch64/sve/pr96974.C
  6c0e94c363caf9e62df35ea98b4918ed  gcc/testsuite/g++.target/aarch64/sve/pr98177-1.C
  e64000c150bb204c31dca884ee33dd4f  gcc/testsuite/g++.target/aarch64/sve/pr98177-2.C
*************** c06d3b2030bc06f25071cbc162980592  gcc/te
*** 55101,55106 ****
--- 55102,55108 ----
  c0b04f74adb90213a554c87f602b9139  gcc/testsuite/gcc.target/aarch64/pr109661-1.c
  7506b184bf1ad4df113825935c38bf26  gcc/testsuite/gcc.target/aarch64/pr112787.c
  5c93b32021bd32ca40c9fb5ec6a30f04  gcc/testsuite/gcc.target/aarch64/pr113552.c
+ 83ac293146b05a62ec4a19e52751ebd1  gcc/testsuite/gcc.target/aarch64/pr121253.c
  9adb42733d9f5e2b1f2dbb364b62100d  gcc/testsuite/gcc.target/aarch64/pr37780_1.c
  e668fb9e0d32efadd671247467dc90db  gcc/testsuite/gcc.target/aarch64/pr58460.c
  9023f817c07ddec673c5b546525fc184  gcc/testsuite/gcc.target/aarch64/pr60034.c
*************** bb3a7f2587d8584d185738649f93a6f6  gcc/te
*** 57666,57671 ****
--- 57668,57674 ----
  6d3b0cbb6b0b88e0030fbf0003faa4c9  gcc/testsuite/gcc.target/aarch64/sve/acle/general/pnext_2.c
  9ff121474de72b7f1e7df15e02d1fcbf  gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr104092.c
  06b9fe18846ba9da10d77ea945b0fa4f  gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr107920.c
+ c1f0d92266055a62f8c3a0b32cffca32  gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr121118_1.c
  cd84e485b3fa7a0d50f2ee5113eca33d  gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr94683.c
  111a35b5bdbe877086a99d29b13dc65b  gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr94700.c
  dd9873ff910539b000561a51ccc3a52f  gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr96146.c
diff -Nrcpad gcc-13-20250814/gcc/ChangeLog gcc-13-20250821/gcc/ChangeLog
*** gcc-13-20250814/gcc/ChangeLog	Thu Aug 14 22:32:05 2025
--- gcc-13-20250821/gcc/ChangeLog	Thu Aug 21 22:32:09 2025
***************
*** 1,3 ****
--- 1,76 ----
+ 2025-08-20  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	Backported from master:
+ 	2025-08-20  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	PR target/121608
+ 	* config/avr/specs.h (LINK_RELAX_SPEC): Wrap in %{!r...}.
+ 
+ 2025-08-18  Richard Sandiford  <richard.sandiford@arm.com>
+ 
+ 	Backported from master:
+ 	2025-08-18  Richard Sandiford  <richard.sandiford@arm.com>
+ 
+ 	PR target/121118
+ 	* config/aarch64/aarch64.cc (aarch64_sve_move_pred_via_while):
+ 	Return a VNx16BI predicate.
+ 
+ 2025-08-18  Richard Sandiford  <richard.sandiford@arm.com>
+ 
+ 	Backported from master:
+ 	2025-08-12  Richard Sandiford  <richard.sandiford@arm.com>
+ 
+ 	PR rtl-optimization/121253
+ 	* fwprop.cc (forward_propagate_into): Don't propagate asm defs.
+ 
+ 2025-08-15  Pengfei Li  <Pengfei.Li2@arm.com>
+ 
+ 	PR target/121449
+ 	* config/aarch64/aarch64-sve.md
+ 	(mask_gather_load<mode><v_int_container>): Use vg<Vesize>
+ 	constraints for alternatives with immediate offset.
+ 	(mask_scatter_store<mode><v_int_container>): Likewise.
+ 
+ 2025-08-14  Richard Sandiford  <richard.sandiford@arm.com>
+ 
+ 	Backported from master:
+ 	2025-08-14  Richard Sandiford  <richard.sandiford@arm.com>
+ 
+ 	PR target/121294
+ 	* config/aarch64/aarch64.md (UNSPEC_REV_PRED): New unspec.
+ 	* config/aarch64/aarch64-sve.md (@aarch64_sve_rev<mode>_acle)
+ 	(*aarch64_sve_rev<mode>_acle): New patterns.
+ 	* config/aarch64/aarch64-sve-builtins-base.cc
+ 	(svrev_impl::expand): Use the new patterns for boolean svrev.
+ 
+ 2025-08-14  Richard Sandiford  <richard.sandiford@arm.com>
+ 
+ 	Backported from master:
+ 	2025-08-14  Richard Sandiford  <richard.sandiford@arm.com>
+ 
+ 	PR target/121294
+ 	* config/aarch64/iterators.md (UNSPEC_TRN1_CONV): Delete.
+ 	(UNSPEC_PERMUTE_PRED): New unspec.
+ 	* config/aarch64/aarch64-sve.md (@aarch64_sve_trn1_conv<mode>):
+ 	Replace with...
+ 	(@aarch64_sve_<perm_insn><mode>_acle)
+ 	(*aarch64_sve_<perm_insn><mode>_acle): ...these new patterns.
+ 	* config/aarch64/aarch64.cc (aarch64_expand_sve_const_pred_trn):
+ 	Update accordingly.
+ 	* config/aarch64/aarch64-sve-builtins-functions.h
+ 	(binary_permute::expand): Use the new _acle patterns for
+ 	predicate operations.
+ 
+ 2025-08-14  H.J. Lu  <hjl.tools@gmail.com>
+ 
+ 	Backported from master:
+ 	2025-07-28  H.J. Lu  <hjl.tools@gmail.com>
+ 
+ 	PR target/121208
+ 	* config/i386/i386.cc (ix86_tls_get_addr): Issue an error for
+ 	-mtls-dialect=gnu with no_caller_saved_registers attribute and
+ 	suggest -mtls-dialect=gnu2.
+ 
  2025-07-31  H.J. Lu  <hjl.tools@gmail.com>
  
  	Backported from master:
diff -Nrcpad gcc-13-20250814/gcc/DATESTAMP gcc-13-20250821/gcc/DATESTAMP
*** gcc-13-20250814/gcc/DATESTAMP	Thu Aug 14 22:32:05 2025
--- gcc-13-20250821/gcc/DATESTAMP	Thu Aug 21 22:32:10 2025
***************
*** 1 ****
! 20250814
--- 1 ----
! 20250821
diff -Nrcpad gcc-13-20250814/gcc/config/aarch64/aarch64-sve.md gcc-13-20250821/gcc/config/aarch64/aarch64-sve.md
*** gcc-13-20250814/gcc/config/aarch64/aarch64-sve.md	Thu Aug 14 22:32:06 2025
--- gcc-13-20250821/gcc/config/aarch64/aarch64-sve.md	Thu Aug 21 22:32:11 2025
***************
*** 1421,1427 ****
    [(set (match_operand:SVE_4 0 "register_operand" "=w, w, w, w, w, w")
  	(unspec:SVE_4
  	  [(match_operand:VNx4BI 5 "register_operand" "Upl, Upl, Upl, Upl, Upl, Upl")
! 	   (match_operand:DI 1 "aarch64_sve_gather_offset_<Vesize>" "Z, vgw, rk, rk, rk, rk")
  	   (match_operand:VNx4SI 2 "register_operand" "w, w, w, w, w, w")
  	   (match_operand:DI 3 "const_int_operand" "Ui1, Ui1, Z, Ui1, Z, Ui1")
  	   (match_operand:DI 4 "aarch64_gather_scale_operand_<Vesize>" "Ui1, Ui1, Ui1, Ui1, i, i")
--- 1421,1427 ----
    [(set (match_operand:SVE_4 0 "register_operand" "=w, w, w, w, w, w")
  	(unspec:SVE_4
  	  [(match_operand:VNx4BI 5 "register_operand" "Upl, Upl, Upl, Upl, Upl, Upl")
! 	   (match_operand:DI 1 "aarch64_sve_gather_offset_<Vesize>" "Z, vg<Vesize>, rk, rk, rk, rk")
  	   (match_operand:VNx4SI 2 "register_operand" "w, w, w, w, w, w")
  	   (match_operand:DI 3 "const_int_operand" "Ui1, Ui1, Z, Ui1, Z, Ui1")
  	   (match_operand:DI 4 "aarch64_gather_scale_operand_<Vesize>" "Ui1, Ui1, Ui1, Ui1, i, i")
***************
*** 1443,1449 ****
    [(set (match_operand:SVE_2 0 "register_operand" "=w, w, w, w")
  	(unspec:SVE_2
  	  [(match_operand:VNx2BI 5 "register_operand" "Upl, Upl, Upl, Upl")
! 	   (match_operand:DI 1 "aarch64_sve_gather_offset_<Vesize>" "Z, vgd, rk, rk")
  	   (match_operand:VNx2DI 2 "register_operand" "w, w, w, w")
  	   (match_operand:DI 3 "const_int_operand")
  	   (match_operand:DI 4 "aarch64_gather_scale_operand_<Vesize>" "Ui1, Ui1, Ui1, i")
--- 1443,1449 ----
    [(set (match_operand:SVE_2 0 "register_operand" "=w, w, w, w")
  	(unspec:SVE_2
  	  [(match_operand:VNx2BI 5 "register_operand" "Upl, Upl, Upl, Upl")
! 	   (match_operand:DI 1 "aarch64_sve_gather_offset_<Vesize>" "Z, vg<Vesize>, rk, rk")
  	   (match_operand:VNx2DI 2 "register_operand" "w, w, w, w")
  	   (match_operand:DI 3 "const_int_operand")
  	   (match_operand:DI 4 "aarch64_gather_scale_operand_<Vesize>" "Ui1, Ui1, Ui1, i")
***************
*** 2254,2260 ****
    [(set (mem:BLK (scratch))
  	(unspec:BLK
  	  [(match_operand:VNx4BI 5 "register_operand" "Upl, Upl, Upl, Upl, Upl, Upl")
! 	   (match_operand:DI 0 "aarch64_sve_gather_offset_<Vesize>" "Z, vgw, rk, rk, rk, rk")
  	   (match_operand:VNx4SI 1 "register_operand" "w, w, w, w, w, w")
  	   (match_operand:DI 2 "const_int_operand" "Ui1, Ui1, Z, Ui1, Z, Ui1")
  	   (match_operand:DI 3 "aarch64_gather_scale_operand_<Vesize>" "Ui1, Ui1, Ui1, Ui1, i, i")
--- 2254,2260 ----
    [(set (mem:BLK (scratch))
  	(unspec:BLK
  	  [(match_operand:VNx4BI 5 "register_operand" "Upl, Upl, Upl, Upl, Upl, Upl")
! 	   (match_operand:DI 0 "aarch64_sve_gather_offset_<Vesize>" "Z, vg<Vesize>, rk, rk, rk, rk")
  	   (match_operand:VNx4SI 1 "register_operand" "w, w, w, w, w, w")
  	   (match_operand:DI 2 "const_int_operand" "Ui1, Ui1, Z, Ui1, Z, Ui1")
  	   (match_operand:DI 3 "aarch64_gather_scale_operand_<Vesize>" "Ui1, Ui1, Ui1, Ui1, i, i")
***************
*** 2276,2282 ****
    [(set (mem:BLK (scratch))
  	(unspec:BLK
  	  [(match_operand:VNx2BI 5 "register_operand" "Upl, Upl, Upl, Upl")
! 	   (match_operand:DI 0 "aarch64_sve_gather_offset_<Vesize>" "Z, vgd, rk, rk")
  	   (match_operand:VNx2DI 1 "register_operand" "w, w, w, w")
  	   (match_operand:DI 2 "const_int_operand")
  	   (match_operand:DI 3 "aarch64_gather_scale_operand_<Vesize>" "Ui1, Ui1, Ui1, i")
--- 2276,2282 ----
    [(set (mem:BLK (scratch))
  	(unspec:BLK
  	  [(match_operand:VNx2BI 5 "register_operand" "Upl, Upl, Upl, Upl")
! 	   (match_operand:DI 0 "aarch64_sve_gather_offset_<Vesize>" "Z, vg<Vesize>, rk, rk")
  	   (match_operand:VNx2DI 1 "register_operand" "w, w, w, w")
  	   (match_operand:DI 2 "const_int_operand")
  	   (match_operand:DI 3 "aarch64_gather_scale_operand_<Vesize>" "Ui1, Ui1, Ui1, i")
diff -Nrcpad gcc-13-20250814/gcc/config/aarch64/aarch64.cc gcc-13-20250821/gcc/config/aarch64/aarch64.cc
*** gcc-13-20250814/gcc/config/aarch64/aarch64.cc	Thu Aug 14 22:32:06 2025
--- gcc-13-20250821/gcc/config/aarch64/aarch64.cc	Thu Aug 21 22:32:11 2025
*************** aarch64_sve_move_pred_via_while (rtx tar
*** 6518,6524 ****
    target = aarch64_target_reg (target, mode);
    emit_insn (gen_while (UNSPEC_WHILELO, DImode, mode,
  			target, const0_rtx, limit));
!   return target;
  }
  
  static rtx
--- 6518,6524 ----
    target = aarch64_target_reg (target, mode);
    emit_insn (gen_while (UNSPEC_WHILELO, DImode, mode,
  			target, const0_rtx, limit));
!   return gen_lowpart (VNx16BImode, target);
  }
  
  static rtx
diff -Nrcpad gcc-13-20250814/gcc/config/avr/specs.h gcc-13-20250821/gcc/config/avr/specs.h
*** gcc-13-20250814/gcc/config/avr/specs.h	Thu Aug 14 22:32:06 2025
--- gcc-13-20250821/gcc/config/avr/specs.h	Thu Aug 21 22:32:11 2025
*************** along with GCC; see the file COPYING3.
*** 59,65 ****
    "%{mmcu=*:-m%*} "
  
  #define LINK_RELAX_SPEC                         \
!   "%{mrelax:--relax} "
  
  #undef  LINK_SPEC
  #define LINK_SPEC                               \
--- 59,65 ----
    "%{mmcu=*:-m%*} "
  
  #define LINK_RELAX_SPEC                         \
!   "%{!r:%{mrelax:--relax}} "
  
  #undef  LINK_SPEC
  #define LINK_SPEC                               \
diff -Nrcpad gcc-13-20250814/gcc/fwprop.cc gcc-13-20250821/gcc/fwprop.cc
*** gcc-13-20250814/gcc/fwprop.cc	Thu Aug 14 22:32:07 2025
--- gcc-13-20250821/gcc/fwprop.cc	Thu Aug 21 22:32:12 2025
*************** forward_propagate_into (use_info *use, b
*** 837,842 ****
--- 837,856 ----
    if (def_insn->is_artificial ())
      return false;
  
+   /* Do not propagate asms.  The only kind of propagation that would
+      succeed is propagation into a register move.  Such a propagation
+      is neutral if the destination of the move is a pseudo and unnecessarily
+      restricts the register allocator if the destination of the move is
+      a hard register.
+ 
+      Furthermore, unlike for a normal instruction, we cannot take a SET from an
+      asm and try dropping the CLOBBERs.  The recog process does not (and should
+      not try to) second-guess whether what the user wrote can be changed and
+      so it has to assume that any asm given to it is a fair reflection of
+      what the user wrote.  */
+   if (def_insn->is_asm ())
+     return false;
+ 
    rtx_insn *def_rtl = def_insn->rtl ();
    if (!NONJUMP_INSN_P (def_rtl))
      return false;
diff -Nrcpad gcc-13-20250814/gcc/testsuite/ChangeLog gcc-13-20250821/gcc/testsuite/ChangeLog
*** gcc-13-20250814/gcc/testsuite/ChangeLog	Thu Aug 14 22:32:08 2025
--- gcc-13-20250821/gcc/testsuite/ChangeLog	Thu Aug 21 22:32:13 2025
***************
*** 1,3 ****
--- 1,68 ----
+ 2025-08-18  Richard Sandiford  <richard.sandiford@arm.com>
+ 
+ 	Backported from master:
+ 	2025-08-18  Richard Sandiford  <richard.sandiford@arm.com>
+ 
+ 	PR target/121118
+ 	* gcc.target/aarch64/sve/acle/general/pr121118_1.c: New test.
+ 
+ 2025-08-18  Richard Sandiford  <richard.sandiford@arm.com>
+ 
+ 	Backported from master:
+ 	2025-08-12  Richard Sandiford  <richard.sandiford@arm.com>
+ 
+ 	PR rtl-optimization/121253
+ 	* gcc.target/aarch64/pr121253.c: New test.
+ 
+ 2025-08-15  Pengfei Li  <Pengfei.Li2@arm.com>
+ 
+ 	PR target/121449
+ 	* g++.target/aarch64/sve/pr121449.C: New test.
+ 
+ 2025-08-14  Richard Sandiford  <richard.sandiford@arm.com>
+ 
+ 	Backported from master:
+ 	2025-08-14  Richard Sandiford  <richard.sandiford@arm.com>
+ 
+ 	PR target/121294
+ 	* gcc.target/aarch64/sve/acle/general/rev_2.c: New test.
+ 
+ 2025-08-14  Richard Sandiford  <richard.sandiford@arm.com>
+ 
+ 	Backported from master:
+ 	2025-08-14  Richard Sandiford  <richard.sandiford@arm.com>
+ 
+ 	PR target/121294
+ 	* gcc.target/aarch64/sve/acle/general/perm_2.c: New test.
+ 	* gcc.target/aarch64/sve/acle/general/perm_3.c: Likewise.
+ 	* gcc.target/aarch64/sve/acle/general/perm_4.c: Likewise.
+ 	* gcc.target/aarch64/sve/acle/general/perm_5.c: Likewise.
+ 	* gcc.target/aarch64/sve/acle/general/perm_6.c: Likewise.
+ 	* gcc.target/aarch64/sve/acle/general/perm_7.c: Likewise.
+ 
+ 2025-08-14  H.J. Lu  <hjl.tools@gmail.com>
+ 
+ 	Backported from master:
+ 	2025-07-29  H.J. Lu  <hjl.tools@gmail.com>
+ 
+ 	PR target/121208
+ 	* gcc.target/i386/pr121208-1a.c (dg-options): Add
+ 	-mno-sse -mno-mmx -mno-80387.
+ 	* gcc.target/i386/pr121208-1b.c (dg-options): Likewise.
+ 
+ 2025-08-14  H.J. Lu  <hjl.tools@gmail.com>
+ 
+ 	Backported from master:
+ 	2025-07-28  H.J. Lu  <hjl.tools@gmail.com>
+ 
+ 	PR target/121208
+ 	* gcc.target/i386/pr121208-1a.c: New test.
+ 	* gcc.target/i386/pr121208-1b.c: Likewise.
+ 	* gcc.target/i386/pr121208-2a.c: Likewise.
+ 	* gcc.target/i386/pr121208-2b.c: Likewise.
+ 	* gcc.target/i386/pr121208-3a.c: Likewise.
+ 	* gcc.target/i386/pr121208-3b.c: Likewise.
+ 
  2025-08-08  Patrick Palka  <ppalka@redhat.com>
  
  	Backported from master:
diff -Nrcpad gcc-13-20250814/gcc/testsuite/g++.target/aarch64/sve/pr121449.C gcc-13-20250821/gcc/testsuite/g++.target/aarch64/sve/pr121449.C
*** gcc-13-20250814/gcc/testsuite/g++.target/aarch64/sve/pr121449.C	Thu Jan  1 00:00:00 1970
--- gcc-13-20250821/gcc/testsuite/g++.target/aarch64/sve/pr121449.C	Thu Aug 21 22:32:19 2025
***************
*** 0 ****
--- 1,44 ----
+ /* PR target/121449 */
+ /* { dg-do assemble { target aarch64_asm_sve_ok } } */
+ /* { dg-options "-O3 -save-temps" } */
+ 
+ struct example;
+ 
+ struct array {
+   unsigned length();
+   example *operator[](unsigned i) {
+     example **data = reinterpret_cast<example **>(this);
+     return data[i];
+   }
+ };
+ 
+ struct example {
+   int a[16];
+   bool is_even;
+   int version;
+   int count() { return is_even ? 2 : 1; }
+   void fun1(int, long);
+   void fun2(unsigned, unsigned);
+   void process(array &, array &);
+ };
+ 
+ bool found;
+ 
+ void example::process(array &a, array &b) {
+   for (unsigned i = 1; a.length(); i++) {
+     long total = 0;
+     for (unsigned k = 0; k <= i; k++) {
+       total += a[k]->count();
+     }
+     for (unsigned j = 0; j < i; j++) {
+       int major = b[j]->version;
+       if (found)
+         major += i;
+       fun1(i + 1, total);
+       fun2(j, major);
+     }
+   }
+ }
+ 
+ /* { dg-final { scan-assembler-not {\tld1b\t(z[0-9]+)\.d, p[0-7]/z, \[(z[0-9]+)\.d, #64\]} } } */
+ 
diff -Nrcpad gcc-13-20250814/gcc/testsuite/gcc.target/aarch64/pr121253.c gcc-13-20250821/gcc/testsuite/gcc.target/aarch64/pr121253.c
*** gcc-13-20250814/gcc/testsuite/gcc.target/aarch64/pr121253.c	Thu Jan  1 00:00:00 1970
--- gcc-13-20250821/gcc/testsuite/gcc.target/aarch64/pr121253.c	Thu Aug 21 22:32:42 2025
***************
*** 0 ****
--- 1,16 ----
+ /* { dg-options "-O" } */
+ 
+ struct s128 {
+     long a, b;
+ };
+ 
+ struct s128 foo(void) {
+     struct s128 ret;
+     asm("mov %0, #0 \n\t"
+         "mov %R0, #0 \n\t"
+         "mov x0, #12345"
+         : "=r" (ret) : : "x0");
+     return ret;
+ }
+ 
+ /* { dg-final { scan-assembler-not {mov x0, #0} } } */
diff -Nrcpad gcc-13-20250814/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr121118_1.c gcc-13-20250821/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr121118_1.c
*** gcc-13-20250814/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr121118_1.c	Thu Jan  1 00:00:00 1970
--- gcc-13-20250821/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr121118_1.c	Thu Aug 21 22:32:43 2025
***************
*** 0 ****
--- 1,16 ----
+ /* { dg-options "-O2 -msve-vector-bits=512" } */
+ 
+ typedef __SVBool_t fixed_bool __attribute__((arm_sve_vector_bits(512)));
+ 
+ #define TEST_CONST(NAME, CONST)						\
+   fixed_bool								\
+   NAME ()								\
+   {									\
+     union { unsigned long long i; fixed_bool pg; } u = { CONST };	\
+     return u.pg;							\
+   }
+ 
+ TEST_CONST (test1, 0x02aaaaaaaa)
+ TEST_CONST (test2, 0x0155555557)
+ TEST_CONST (test3, 0x0013333333333333ULL)
+ TEST_CONST (test4, 0x0011111111111113ULL)
