diff -Nrcpad gcc-13-20250911/LAST_UPDATED gcc-13-20250918/LAST_UPDATED
*** gcc-13-20250911/LAST_UPDATED	Thu Sep 11 22:33:28 2025
--- gcc-13-20250918/LAST_UPDATED	Thu Sep 18 22:33:45 2025
***************
*** 1 ****
! Obtained from git: releases/gcc-13 revision c9e85072cbfc6740360a9f230832054f788d23e4
--- 1 ----
! Obtained from git: releases/gcc-13 revision b748d6f63cb87a7d78a1d41f98a5763bbadd4d03
diff -Nrcpad gcc-13-20250911/MD5SUMS gcc-13-20250918/MD5SUMS
*** gcc-13-20250911/MD5SUMS	Thu Sep 11 22:33:37 2025
--- gcc-13-20250918/MD5SUMS	Thu Sep 18 22:33:55 2025
***************
*** 1,5 ****
  # This file contains the MD5 checksums of the files in the
! # gcc-13-20250911.tar.xz tarball.
  #
  # Besides verifying that all files in the tarball were correctly expanded,
  # it also can be used to determine if any files have changed since the
--- 1,5 ----
  # This file contains the MD5 checksums of the files in the
! # gcc-13-20250918.tar.xz tarball.
  #
  # Besides verifying that all files in the tarball were correctly expanded,
  # it also can be used to determine if any files have changed since the
*************** d32239bcb673463ab874e80d47fae504  COPYIN
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*************** a92be6f532ece352cab8309520cf28f0  gcc/co
*** 5078,5084 ****
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*** 5150,5156 ****
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*************** e927561ee87ffd471419ab7c04a9c03d  gcc/di
*** 5458,5464 ****
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--- 5458,5464 ----
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*************** fdb910a61276129e6981a007c1cd94f6  gcc/lo
*** 6116,6122 ****
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--- 6116,6122 ----
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*************** b829ed0032c899e107be2db349c913f3  gcc/ta
*** 7637,7643 ****
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*** 12825,12830 ****
--- 12825,12831 ----
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*************** c6848ef9d4a9873e77016b18db0eef64  gcc/te
*** 49889,49894 ****
--- 49890,49897 ----
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*************** cbaafd43310e10a7ba4ce687bafe06da  gcc/te
*** 69722,69732 ****
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--- 69725,69735 ----
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*************** b9528f9fe022aa90d7c7d9764f67ece4  gcc/te
*** 69775,69784 ****
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--- 69778,69787 ----
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*************** feca017a2b8993f6879429c3b7fa9740  gcc/tr
*** 100473,100479 ****
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  1f7981f8ac0c98c7d1acb674035e2c16  gcc/tree-sra.h
  931fca6fc15298fa1f2021f8e4f2ed8d  gcc/tree-ssa-address.cc
  c37e139873f3e8da2fffefa09903ee42  gcc/tree-ssa-address.h
--- 100476,100482 ----
  13e933e748d0799695ef67be87740769  gcc/tree-profile.cc
  835e107c7d950e109cab7dc47dd27a51  gcc/tree-scalar-evolution.cc
  b8223329488a4001552728350c5dbbef  gcc/tree-scalar-evolution.h
! 5e677b9e7eeb0dadfa42a9dae0095eed  gcc/tree-sra.cc
  1f7981f8ac0c98c7d1acb674035e2c16  gcc/tree-sra.h
  931fca6fc15298fa1f2021f8e4f2ed8d  gcc/tree-ssa-address.cc
  c37e139873f3e8da2fffefa09903ee42  gcc/tree-ssa-address.h
diff -Nrcpad gcc-13-20250911/gcc/ChangeLog gcc-13-20250918/gcc/ChangeLog
*** gcc-13-20250911/gcc/ChangeLog	Thu Sep 11 22:32:06 2025
--- gcc-13-20250918/gcc/ChangeLog	Thu Sep 18 22:32:18 2025
***************
*** 1,3 ****
--- 1,37 ----
+ 2025-09-17  Martin Jambor  <mjambor@suse.cz>
+ 
+ 	Backported from master:
+ 	2025-08-20  Martin Jambor  <mjambor@suse.cz>
+ 
+ 	PR tree-optimization/119085
+ 	* tree-sra.cc (sort_and_splice_var_accesses): Prevent total
+ 	scalarization if two incompatible aggregates access the same place.
+ 
+ 2025-09-17  Martin Jambor  <mjambor@suse.cz>
+ 
+ 	Backported from master:
+ 	2025-09-17  Martin Jambor  <mjambor@suse.cz>
+ 
+ 	PR tree-optimization/117423
+ 	* tree-sra.cc (analyze_access_subtree): Fix computation of grp_covered
+ 	flag.
+ 
+ 2025-09-16  Jeff Law  <jlaw@ventanamicro.com>
+ 
+ 	Backported from master:
+ 	2025-09-12  Jeff Law  <jlaw@ventanamicro.com>
+ 
+ 	* lra-constraints.cc (get_equiv): Bounds check before accessing
+ 	data in ira_reg_equiv.
+ 
+ 2025-09-15  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	* config/avr/avr-mcus.def: Support AVR32DA28S, AVR32DA32S,
+ 	AVR32DA48S, AVR64DA28S, AVR64DA32S, AVR64DA48S AVR64DA64S,
+ 	AVR128DA28S, AVR128DA32S, AVR128DA48S, AVR128DA64S,
+ 	AVR32EB14, AVR32EB20, AVR32EB28, AVR32EB32.
+ 	* doc/avr-mmcu.texi: Rebuild.
+ 
  2025-09-10  Georg-Johann Lay  <avr@gjlay.de>
  
  	Backported from master:
diff -Nrcpad gcc-13-20250911/gcc/DATESTAMP gcc-13-20250918/gcc/DATESTAMP
*** gcc-13-20250911/gcc/DATESTAMP	Thu Sep 11 22:32:06 2025
--- gcc-13-20250918/gcc/DATESTAMP	Thu Sep 18 22:32:18 2025
***************
*** 1 ****
! 20250911
--- 1 ----
! 20250918
diff -Nrcpad gcc-13-20250911/gcc/config/avr/avr-mcus.def gcc-13-20250918/gcc/config/avr/avr-mcus.def
*** gcc-13-20250911/gcc/config/avr/avr-mcus.def	Thu Sep 11 22:32:07 2025
--- gcc-13-20250918/gcc/config/avr/avr-mcus.def	Thu Sep 18 22:32:19 2025
*************** AVR_MCU ("avr64da28",        ARCH_AVRXME
*** 313,318 ****
--- 313,322 ----
  AVR_MCU ("avr64da32",        ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_AVR64DA32__",    0x6000, 0x0, 0x10000, 0)
  AVR_MCU ("avr64da48",        ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_AVR64DA48__",    0x6000, 0x0, 0x10000, 0)
  AVR_MCU ("avr64da64",        ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_AVR64DA64__",    0x6000, 0x0, 0x10000, 0)
+ AVR_MCU ("avr64da28s",       ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_AVR64DA28S__",   0x6000, 0x0, 0x10000, 0)
+ AVR_MCU ("avr64da32s",       ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_AVR64DA32S__",   0x6000, 0x0, 0x10000, 0)
+ AVR_MCU ("avr64da48s",       ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_AVR64DA48S__",   0x6000, 0x0, 0x10000, 0)
+ AVR_MCU ("avr64da64s",       ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_AVR64DA64S__",   0x6000, 0x0, 0x10000, 0)
  AVR_MCU ("avr64db28",        ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_AVR64DB28__",    0x6000, 0x0, 0x10000, 0)
  AVR_MCU ("avr64db32",        ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_AVR64DB32__",    0x6000, 0x0, 0x10000, 0)
  AVR_MCU ("avr64db48",        ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_AVR64DB48__",    0x6000, 0x0, 0x10000, 0)
*************** AVR_MCU ("avr16du32",        ARCH_AVRXME
*** 389,394 ****
--- 393,401 ----
  AVR_MCU ("avr32da28",        ARCH_AVRXMEGA3, AVR_ISA_NONE,  "__AVR_AVR32DA28__",   0x7000, 0x0, 0x8000, 0x8000)
  AVR_MCU ("avr32da32",        ARCH_AVRXMEGA3, AVR_ISA_NONE,  "__AVR_AVR32DA32__",   0x7000, 0x0, 0x8000, 0x8000)
  AVR_MCU ("avr32da48",        ARCH_AVRXMEGA3, AVR_ISA_NONE,  "__AVR_AVR32DA48__",   0x7000, 0x0, 0x8000, 0x8000)
+ AVR_MCU ("avr32da28s",       ARCH_AVRXMEGA3, AVR_ISA_NONE,  "__AVR_AVR32DA28S__",  0x7000, 0x0, 0x8000, 0x8000)
+ AVR_MCU ("avr32da32s",       ARCH_AVRXMEGA3, AVR_ISA_NONE,  "__AVR_AVR32DA32S__",  0x7000, 0x0, 0x8000, 0x8000)
+ AVR_MCU ("avr32da48s",       ARCH_AVRXMEGA3, AVR_ISA_NONE,  "__AVR_AVR32DA48S__",  0x7000, 0x0, 0x8000, 0x8000)
  AVR_MCU ("avr32db28",        ARCH_AVRXMEGA3, AVR_ISA_NONE,  "__AVR_AVR32DB28__",   0x7000, 0x0, 0x8000, 0x8000)
  AVR_MCU ("avr32db32",        ARCH_AVRXMEGA3, AVR_ISA_NONE,  "__AVR_AVR32DB32__",   0x7000, 0x0, 0x8000, 0x8000)
  AVR_MCU ("avr32db48",        ARCH_AVRXMEGA3, AVR_ISA_NONE,  "__AVR_AVR32DB48__",   0x7000, 0x0, 0x8000, 0x8000)
*************** AVR_MCU ("avr16eb14",        ARCH_AVRXME
*** 404,409 ****
--- 411,420 ----
  AVR_MCU ("avr16eb20",        ARCH_AVRXMEGA3, AVR_ISA_NONE,  "__AVR_AVR16EB20__",   0x7800, 0x0, 0x4000, 0x8000)
  AVR_MCU ("avr16eb28",        ARCH_AVRXMEGA3, AVR_ISA_NONE,  "__AVR_AVR16EB28__",   0x7800, 0x0, 0x4000, 0x8000)
  AVR_MCU ("avr16eb32",        ARCH_AVRXMEGA3, AVR_ISA_NONE,  "__AVR_AVR16EB32__",   0x7800, 0x0, 0x4000, 0x8000)
+ AVR_MCU ("avr32eb14",        ARCH_AVRXMEGA3, AVR_ISA_NONE,  "__AVR_AVR32EB14__",   0x7400, 0x0, 0x8000, 0x8000)
+ AVR_MCU ("avr32eb20",        ARCH_AVRXMEGA3, AVR_ISA_NONE,  "__AVR_AVR32EB20__",   0x7400, 0x0, 0x8000, 0x8000)
+ AVR_MCU ("avr32eb28",        ARCH_AVRXMEGA3, AVR_ISA_NONE,  "__AVR_AVR32EB28__",   0x7400, 0x0, 0x8000, 0x8000)
+ AVR_MCU ("avr32eb32",        ARCH_AVRXMEGA3, AVR_ISA_NONE,  "__AVR_AVR32EB32__",   0x7400, 0x0, 0x8000, 0x8000)
  AVR_MCU ("avr16ea28",        ARCH_AVRXMEGA3, AVR_ISA_NONE,  "__AVR_AVR16EA28__",   0x7800, 0x0, 0x4000, 0x8000)
  AVR_MCU ("avr16ea32",        ARCH_AVRXMEGA3, AVR_ISA_NONE,  "__AVR_AVR16EA32__",   0x7800, 0x0, 0x4000, 0x8000)
  AVR_MCU ("avr16ea48",        ARCH_AVRXMEGA3, AVR_ISA_NONE,  "__AVR_AVR16EA48__",   0x7800, 0x0, 0x4000, 0x8000)
*************** AVR_MCU ("avr128da28",       ARCH_AVRXME
*** 427,432 ****
--- 438,447 ----
  AVR_MCU ("avr128da32",       ARCH_AVRXMEGA4, AVR_ISA_NONE, "__AVR_AVR128DA32__",   0x4000, 0x0, 0x20000, 0)
  AVR_MCU ("avr128da48",       ARCH_AVRXMEGA4, AVR_ISA_NONE, "__AVR_AVR128DA48__",   0x4000, 0x0, 0x20000, 0)
  AVR_MCU ("avr128da64",       ARCH_AVRXMEGA4, AVR_ISA_NONE, "__AVR_AVR128DA64__",   0x4000, 0x0, 0x20000, 0)
+ AVR_MCU ("avr128da28s",      ARCH_AVRXMEGA4, AVR_ISA_NONE, "__AVR_AVR128DA28S__",  0x4000, 0x0, 0x20000, 0)
+ AVR_MCU ("avr128da32s",      ARCH_AVRXMEGA4, AVR_ISA_NONE, "__AVR_AVR128DA32S__",  0x4000, 0x0, 0x20000, 0)
+ AVR_MCU ("avr128da48s",      ARCH_AVRXMEGA4, AVR_ISA_NONE, "__AVR_AVR128DA48S__",  0x4000, 0x0, 0x20000, 0)
+ AVR_MCU ("avr128da64s",      ARCH_AVRXMEGA4, AVR_ISA_NONE, "__AVR_AVR128DA64S__",  0x4000, 0x0, 0x20000, 0)
  AVR_MCU ("avr128db28",       ARCH_AVRXMEGA4, AVR_ISA_NONE, "__AVR_AVR128DB28__",   0x4000, 0x0, 0x20000, 0)
  AVR_MCU ("avr128db32",       ARCH_AVRXMEGA4, AVR_ISA_NONE, "__AVR_AVR128DB32__",   0x4000, 0x0, 0x20000, 0)
  AVR_MCU ("avr128db48",       ARCH_AVRXMEGA4, AVR_ISA_NONE, "__AVR_AVR128DB48__",   0x4000, 0x0, 0x20000, 0)
diff -Nrcpad gcc-13-20250911/gcc/config/i386/x86-tune.def gcc-13-20250918/gcc/config/i386/x86-tune.def
*** gcc-13-20250911/gcc/config/i386/x86-tune.def	Thu Sep 11 22:32:07 2025
--- gcc-13-20250918/gcc/config/i386/x86-tune.def	Thu Sep 18 22:32:19 2025
*************** DEF_TUNE (X86_TUNE_AVX256_AVOID_VEC_PERM
*** 577,582 ****
--- 577,584 ----
  /* X86_TUNE_AVX256_SPLIT_REGS: if true, AVX512 ops are split into two AVX256 ops.  */
  DEF_TUNE (X86_TUNE_AVX512_SPLIT_REGS, "avx512_split_regs", m_ZNVER4)
  
+ /* It's better to align MOVE_MAX with prefer_vector_width to reduce
+    risk of STLF stalls(small store followed by big load.)  */
  /* X86_TUNE_AVX256_MOVE_BY_PIECES: Optimize move_by_pieces with 256-bit
     AVX instructions.  */
  DEF_TUNE (X86_TUNE_AVX256_MOVE_BY_PIECES, "avx256_move_by_pieces",
*************** DEF_TUNE (X86_TUNE_AVX256_STORE_BY_PIECE
*** 590,603 ****
  /* X86_TUNE_AVX512_MOVE_BY_PIECES: Optimize move_by_pieces with 512-bit
     AVX instructions.  */
  DEF_TUNE (X86_TUNE_AVX512_MOVE_BY_PIECES, "avx512_move_by_pieces",
! 	  m_SAPPHIRERAPIDS | m_GRANITERAPIDS | m_GRANITERAPIDS_D
! 	  | m_ZNVER4 | m_ZNVER5)
  
  /* X86_TUNE_AVX512_STORE_BY_PIECES: Optimize store_by_pieces with 512-bit
     AVX instructions.  */
  DEF_TUNE (X86_TUNE_AVX512_STORE_BY_PIECES, "avx512_store_by_pieces",
! 	  m_SAPPHIRERAPIDS | m_GRANITERAPIDS | m_GRANITERAPIDS_D
! 	  | m_ZNVER4 | m_ZNVER5)
  
  /*****************************************************************************/
  /*****************************************************************************/
--- 592,603 ----
  /* X86_TUNE_AVX512_MOVE_BY_PIECES: Optimize move_by_pieces with 512-bit
     AVX instructions.  */
  DEF_TUNE (X86_TUNE_AVX512_MOVE_BY_PIECES, "avx512_move_by_pieces",
! 	   m_ZNVER4 | m_ZNVER5)
  
  /* X86_TUNE_AVX512_STORE_BY_PIECES: Optimize store_by_pieces with 512-bit
     AVX instructions.  */
  DEF_TUNE (X86_TUNE_AVX512_STORE_BY_PIECES, "avx512_store_by_pieces",
! 	  m_ZNVER4 | m_ZNVER5)
  
  /*****************************************************************************/
  /*****************************************************************************/
diff -Nrcpad gcc-13-20250911/gcc/cp/ChangeLog gcc-13-20250918/gcc/cp/ChangeLog
*** gcc-13-20250911/gcc/cp/ChangeLog	Thu Sep 11 22:32:07 2025
--- gcc-13-20250918/gcc/cp/ChangeLog	Thu Sep 18 22:32:19 2025
***************
*** 1,3 ****
--- 1,12 ----
+ 2025-09-15  Matthias Kretz  <m.kretz@gsi.de>
+ 
+ 	Backported from master:
+ 	2025-09-09  Matthias Kretz  <m.kretz@gsi.de>
+ 
+ 	PR c++/121801
+ 	* mangle.cc (write_real_cst): Handle 16-bit real and assert
+ 	that reals have 16 bits or a multiple of 32 bits.
+ 
  2025-08-08  Patrick Palka  <ppalka@redhat.com>
  
  	Backported from master:
diff -Nrcpad gcc-13-20250911/gcc/cp/mangle.cc gcc-13-20250918/gcc/cp/mangle.cc
*** gcc-13-20250911/gcc/cp/mangle.cc	Thu Sep 11 22:32:07 2025
--- gcc-13-20250918/gcc/cp/mangle.cc	Thu Sep 18 22:32:19 2025
*************** write_real_cst (const tree value)
*** 1999,2009 ****
    int i, limit, dir;
  
    tree type = TREE_TYPE (value);
!   int words = GET_MODE_BITSIZE (SCALAR_FLOAT_TYPE_MODE (type)) / 32;
  
    real_to_target (target_real, &TREE_REAL_CST (value),
  		  TYPE_MODE (type));
  
    /* The value in target_real is in the target word order,
       so we must write it out backward if that happens to be
       little-endian.  write_number cannot be used, it will
--- 1999,2022 ----
    int i, limit, dir;
  
    tree type = TREE_TYPE (value);
!   int bits = GET_MODE_BITSIZE (SCALAR_FLOAT_TYPE_MODE (type));
!   int words = bits / 32;
  
    real_to_target (target_real, &TREE_REAL_CST (value),
  		  TYPE_MODE (type));
  
+   if (words == 0)
+     {
+       /* _Float16 and std::bfloat16_t are the only supported types smaller than
+ 	 32 bits.  */
+       gcc_assert (bits == 16);
+       sprintf (buffer, "%04lx", (unsigned long) target_real[0]);
+       write_chars (buffer, 4);
+       return;
+     }
+ 
+   gcc_assert (bits % 32 == 0);
+ 
    /* The value in target_real is in the target word order,
       so we must write it out backward if that happens to be
       little-endian.  write_number cannot be used, it will
diff -Nrcpad gcc-13-20250911/gcc/doc/avr-mmcu.texi gcc-13-20250918/gcc/doc/avr-mmcu.texi
*** gcc-13-20250911/gcc/doc/avr-mmcu.texi	Thu Sep 11 22:32:07 2025
--- gcc-13-20250918/gcc/doc/avr-mmcu.texi	Thu Sep 18 22:32:19 2025
***************
*** 50,64 ****
  
  @item avrxmega2
  ``XMEGA'' devices with more than 8@tie{}KiB and up to 64@tie{}KiB of program memory.
! @*@var{mcu}@tie{}= @code{atxmega8e5}, @code{atxmega16a4}, @code{atxmega16a4u}, @code{atxmega16c4}, @code{atxmega16d4}, @code{atxmega16e5}, @code{atxmega32a4}, @code{atxmega32a4u}, @code{atxmega32c3}, @code{atxmega32c4}, @code{atxmega32d3}, @code{atxmega32d4}, @code{atxmega32e5}, @code{avr64da28}, @code{avr64da32}, @code{avr64da48}, @code{avr64da64}, @code{avr64db28}, @code{avr64db32}, @code{avr64db48}, @code{avr64db64}, @code{avr64dd14}, @code{avr64dd20}, @code{avr64dd28}, @code{avr64dd32}, @code{avr64du28}, @code{avr64du32}, @code{avr64ea28}, @code{avr64ea32}, @code{avr64ea48}, @code{avr64sd28}, @code{avr64sd32}, @code{avr64sd48}.
  
  @item avrxmega3
  ``XMEGA'' devices with up to 64@tie{}KiB of combined program memory and RAM, and with program memory visible in the RAM address space.
! @*@var{mcu}@tie{}= @code{attiny202}, @code{attiny204}, @code{attiny212}, @code{attiny214}, @code{attiny402}, @code{attiny404}, @code{attiny406}, @code{attiny412}, @code{attiny414}, @code{attiny416}, @code{attiny416auto}, @code{attiny417}, @code{attiny424}, @code{attiny426}, @code{attiny427}, @code{attiny804}, @code{attiny806}, @code{attiny807}, @code{attiny814}, @code{attiny816}, @code{attiny817}, @code{attiny824}, @code{attiny826}, @code{attiny827}, @code{attiny1604}, @code{attiny1606}, @code{attiny1607}, @code{attiny1614}, @code{attiny1616}, @code{attiny1617}, @code{attiny1624}, @code{attiny1626}, @code{attiny1627}, @code{attiny3214}, @code{attiny3216}, @code{attiny3217}, @code{attiny3224}, @code{attiny3226}, @code{attiny3227}, @code{atmega808}, @code{atmega809}, @code{atmega1608}, @code{atmega1609}, @code{atmega3208}, @code{atmega3209}, @code{atmega4808}, @code{atmega4809}, @code{avr16dd14}, @code{avr16dd20}, @code{avr16dd28}, @code{avr16dd32}, @code{avr16du14}, @code{avr16du20}, @code{avr16du28}, @code{avr16du32}, @code{avr16ea28}, @code{avr16ea32}, @code{avr16ea48}, @code{avr16eb14}, @code{avr16eb20}, @code{avr16eb28}, @code{avr16eb32}, @code{avr32da28}, @code{avr32da32}, @code{avr32da48}, @code{avr32db28}, @code{avr32db32}, @code{avr32db48}, @code{avr32dd14}, @code{avr32dd20}, @code{avr32dd28}, @code{avr32dd32}, @code{avr32du14}, @code{avr32du20}, @code{avr32du28}, @code{avr32du32}, @code{avr32ea28}, @code{avr32ea32}, @code{avr32ea48}, @code{avr32sd20}, @code{avr32sd28}, @code{avr32sd32}.
  
  @item avrxmega4
  ``XMEGA'' devices with more than 64@tie{}KiB and up to 128@tie{}KiB of program memory.
! @*@var{mcu}@tie{}= @code{atxmega64a3}, @code{atxmega64a3u}, @code{atxmega64a4u}, @code{atxmega64b1}, @code{atxmega64b3}, @code{atxmega64c3}, @code{atxmega64d3}, @code{atxmega64d4}, @code{avr128da28}, @code{avr128da32}, @code{avr128da48}, @code{avr128da64}, @code{avr128db28}, @code{avr128db32}, @code{avr128db48}, @code{avr128db64}.
  
  @item avrxmega5
  ``XMEGA'' devices with more than 64@tie{}KiB and up to 128@tie{}KiB of program memory and more than 64@tie{}KiB of RAM.
--- 50,64 ----
  
  @item avrxmega2
  ``XMEGA'' devices with more than 8@tie{}KiB and up to 64@tie{}KiB of program memory.
! @*@var{mcu}@tie{}= @code{atxmega8e5}, @code{atxmega16a4}, @code{atxmega16a4u}, @code{atxmega16c4}, @code{atxmega16d4}, @code{atxmega16e5}, @code{atxmega32a4}, @code{atxmega32a4u}, @code{atxmega32c3}, @code{atxmega32c4}, @code{atxmega32d3}, @code{atxmega32d4}, @code{atxmega32e5}, @code{avr64da28}, @code{avr64da28s}, @code{avr64da32}, @code{avr64da32s}, @code{avr64da48}, @code{avr64da48s}, @code{avr64da64}, @code{avr64da64s}, @code{avr64db28}, @code{avr64db32}, @code{avr64db48}, @code{avr64db64}, @code{avr64dd14}, @code{avr64dd20}, @code{avr64dd28}, @code{avr64dd32}, @code{avr64du28}, @code{avr64du32}, @code{avr64ea28}, @code{avr64ea32}, @code{avr64ea48}, @code{avr64sd28}, @code{avr64sd32}, @code{avr64sd48}.
  
  @item avrxmega3
  ``XMEGA'' devices with up to 64@tie{}KiB of combined program memory and RAM, and with program memory visible in the RAM address space.
! @*@var{mcu}@tie{}= @code{attiny202}, @code{attiny204}, @code{attiny212}, @code{attiny214}, @code{attiny402}, @code{attiny404}, @code{attiny406}, @code{attiny412}, @code{attiny414}, @code{attiny416}, @code{attiny416auto}, @code{attiny417}, @code{attiny424}, @code{attiny426}, @code{attiny427}, @code{attiny804}, @code{attiny806}, @code{attiny807}, @code{attiny814}, @code{attiny816}, @code{attiny817}, @code{attiny824}, @code{attiny826}, @code{attiny827}, @code{attiny1604}, @code{attiny1606}, @code{attiny1607}, @code{attiny1614}, @code{attiny1616}, @code{attiny1617}, @code{attiny1624}, @code{attiny1626}, @code{attiny1627}, @code{attiny3214}, @code{attiny3216}, @code{attiny3217}, @code{attiny3224}, @code{attiny3226}, @code{attiny3227}, @code{atmega808}, @code{atmega809}, @code{atmega1608}, @code{atmega1609}, @code{atmega3208}, @code{atmega3209}, @code{atmega4808}, @code{atmega4809}, @code{avr16dd14}, @code{avr16dd20}, @code{avr16dd28}, @code{avr16dd32}, @code{avr16du14}, @code{avr16du20}, @code{avr16du28}, @code{avr16du32}, @code{avr16ea28}, @code{avr16ea32}, @code{avr16ea48}, @code{avr16eb14}, @code{avr16eb20}, @code{avr16eb28}, @code{avr16eb32}, @code{avr32da28}, @code{avr32da28s}, @code{avr32da32}, @code{avr32da32s}, @code{avr32da48}, @code{avr32da48s}, @code{avr32db28}, @code{avr32db32}, @code{avr32db48}, @code{avr32dd14}, @code{avr32dd20}, @code{avr32dd28}, @code{avr32dd32}, @code{avr32du14}, @code{avr32du20}, @code{avr32du28}, @code{avr32du32}, @code{avr32ea28}, @code{avr32ea32}, @code{avr32ea48}, @code{avr32eb14}, @code{avr32eb20}, @code{avr32eb28}, @code{avr32eb32}, @code{avr32sd20}, @code{avr32sd28}, @code{avr32sd32}.
  
  @item avrxmega4
  ``XMEGA'' devices with more than 64@tie{}KiB and up to 128@tie{}KiB of program memory.
! @*@var{mcu}@tie{}= @code{atxmega64a3}, @code{atxmega64a3u}, @code{atxmega64a4u}, @code{atxmega64b1}, @code{atxmega64b3}, @code{atxmega64c3}, @code{atxmega64d3}, @code{atxmega64d4}, @code{avr128da28}, @code{avr128da28s}, @code{avr128da32}, @code{avr128da32s}, @code{avr128da48}, @code{avr128da48s}, @code{avr128da64}, @code{avr128da64s}, @code{avr128db28}, @code{avr128db32}, @code{avr128db48}, @code{avr128db64}.
  
  @item avrxmega5
  ``XMEGA'' devices with more than 64@tie{}KiB and up to 128@tie{}KiB of program memory and more than 64@tie{}KiB of RAM.
diff -Nrcpad gcc-13-20250911/gcc/lra-constraints.cc gcc-13-20250918/gcc/lra-constraints.cc
*** gcc-13-20250911/gcc/lra-constraints.cc	Thu Sep 11 22:32:08 2025
--- gcc-13-20250918/gcc/lra-constraints.cc	Thu Sep 18 22:32:20 2025
*************** get_equiv (rtx x)
*** 518,523 ****
--- 518,524 ----
    rtx res;
  
    if (! REG_P (x) || (regno = REGNO (x)) < FIRST_PSEUDO_REGISTER
+       || regno >= ira_reg_equiv_len
        || ! ira_reg_equiv[regno].defined_p
        || ! ira_reg_equiv[regno].profitable_p
        || lra_get_regno_hard_regno (regno) >= 0)
diff -Nrcpad gcc-13-20250911/gcc/testsuite/ChangeLog gcc-13-20250918/gcc/testsuite/ChangeLog
*** gcc-13-20250911/gcc/testsuite/ChangeLog	Thu Sep 11 22:32:08 2025
--- gcc-13-20250918/gcc/testsuite/ChangeLog	Thu Sep 18 22:32:21 2025
***************
*** 1,3 ****
--- 1,27 ----
+ 2025-09-17  Martin Jambor  <mjambor@suse.cz>
+ 
+ 	Backported from master:
+ 	2025-08-20  Martin Jambor  <mjambor@suse.cz>
+ 
+ 	PR tree-optimization/119085
+ 	* gcc.dg/tree-ssa/pr119085.c: New test.
+ 
+ 2025-09-17  Martin Jambor  <mjambor@suse.cz>
+ 
+ 	Backported from master:
+ 	2025-09-17  Martin Jambor  <mjambor@suse.cz>
+ 
+ 	PR tree-optimization/117423
+ 	* gcc.dg/tree-ssa/pr117423.c: New test.
+ 
+ 2025-09-15  Matthias Kretz  <m.kretz@gsi.de>
+ 
+ 	Backported from master:
+ 	2025-09-09  Matthias Kretz  <m.kretz@gsi.de>
+ 
+ 	PR c++/121801
+ 	* g++.dg/abi/pr121801.C: New test.
+ 
  2025-08-30  liuhongt  <hongtao.liu@intel.com>
  
  	Revert:
diff -Nrcpad gcc-13-20250911/gcc/testsuite/g++.dg/abi/pr121801.C gcc-13-20250918/gcc/testsuite/g++.dg/abi/pr121801.C
*** gcc-13-20250911/gcc/testsuite/g++.dg/abi/pr121801.C	Thu Jan  1 00:00:00 1970
--- gcc-13-20250918/gcc/testsuite/g++.dg/abi/pr121801.C	Thu Sep 18 22:32:26 2025
***************
*** 0 ****
--- 1,13 ----
+ // PR c++/121801
+ // { dg-do compile { target { c++20 && float16 } } }
+ // { dg-add-options float16 }
+ 
+ template<_Float16 T> void f() {}
+ 
+ void uses() {
+   f<_Float16(1)>();
+   f<_Float16(2)>();
+ }
+ 
+ // { dg-final { scan-assembler "_Z1fILDF16_3c00EEvv" } }
+ // { dg-final { scan-assembler "_Z1fILDF16_4000EEvv" } }
diff -Nrcpad gcc-13-20250911/gcc/testsuite/gcc.dg/tree-ssa/pr117423.c gcc-13-20250918/gcc/testsuite/gcc.dg/tree-ssa/pr117423.c
*** gcc-13-20250911/gcc/testsuite/gcc.dg/tree-ssa/pr117423.c	Thu Jan  1 00:00:00 1970
--- gcc-13-20250918/gcc/testsuite/gcc.dg/tree-ssa/pr117423.c	Thu Sep 18 22:32:42 2025
***************
*** 0 ****
--- 1,49 ----
+ /* { dg-do run } */
+ /* { dg-options "-O1" } */
+ 
+ struct s4 {
+     int _0;
+ };
+ struct s1 {
+     unsigned char _4;
+     long _1;
+ };
+ struct s2 {
+     union {
+         struct s3 {
+             unsigned char _1;
+             struct s4 _0;
+         } var_0;
+         struct s1 var_1;
+     } DATA;
+ };
+ int f1(int arg0) { return arg0 > 12345; }
+ __attribute__((noinline))
+ struct s4 f2(int arg0) {
+     struct s4 rv = {arg0};
+     return rv;
+ }
+ struct s2 f3(int arg0) {
+     struct s2 rv;
+     struct s1 var6 = {0};
+     struct s4 var7;
+     if (f1(arg0)) {
+         rv.DATA.var_1 = var6;
+         return rv;
+     } else {
+         rv.DATA.var_0._1 = 2;
+         var7 = f2(arg0);
+         rv.DATA.var_0._0 = var7;
+         return rv;
+     }
+ }
+ int main() {
+   if (f3(12345).DATA.var_0._0._0 == 12345)
+     ;
+   else
+     __builtin_abort();
+   if (f3(12344).DATA.var_0._0._0 == 12344)
+     ;
+   else
+     __builtin_abort();
+ }
diff -Nrcpad gcc-13-20250911/gcc/testsuite/gcc.dg/tree-ssa/pr119085.c gcc-13-20250918/gcc/testsuite/gcc.dg/tree-ssa/pr119085.c
*** gcc-13-20250911/gcc/testsuite/gcc.dg/tree-ssa/pr119085.c	Thu Jan  1 00:00:00 1970
--- gcc-13-20250918/gcc/testsuite/gcc.dg/tree-ssa/pr119085.c	Thu Sep 18 22:32:42 2025
***************
*** 0 ****
--- 1,37 ----
+ /* { dg-do run } */
+ /* { dg-options "-O1" } */
+ 
+ struct with_hole {
+   int x;
+   long y;
+ };
+ struct without_hole {
+   int x;
+   int y;
+ };
+ union u {
+   struct with_hole with_hole;
+   struct without_hole without_hole;
+ };
+ 
+ void __attribute__((noinline))
+ test (union u *up, union u u)
+ {
+   union u u2;
+   volatile int f = 0;
+   u2 = u;
+   if (f)
+     u2.with_hole = u.with_hole;
+   *up = u2;
+ }
+ 
+ int main(void)
+ {
+   union u u;
+   union u u2;
+   u2.without_hole.y = -1;
+   test (&u, u2);
+   if (u.without_hole.y != -1)
+     __builtin_abort ();
+   return 0;
+ }
diff -Nrcpad gcc-13-20250911/gcc/testsuite/gcc.target/i386/pieces-memcpy-18.c gcc-13-20250918/gcc/testsuite/gcc.target/i386/pieces-memcpy-18.c
*** gcc-13-20250911/gcc/testsuite/gcc.target/i386/pieces-memcpy-18.c	Thu Sep 11 22:32:21 2025
--- gcc-13-20250918/gcc/testsuite/gcc.target/i386/pieces-memcpy-18.c	Thu Sep 18 22:32:53 2025
***************
*** 1,5 ****
  /* { dg-do compile } */
! /* { dg-options "-O2 -march=sapphirerapids" } */
  
  extern char *dst, *src;
  
--- 1,5 ----
  /* { dg-do compile } */
! /* { dg-options "-O2 -march=znver5" } */
  
  extern char *dst, *src;
  
diff -Nrcpad gcc-13-20250911/gcc/testsuite/gcc.target/i386/pieces-memcpy-21.c gcc-13-20250918/gcc/testsuite/gcc.target/i386/pieces-memcpy-21.c
*** gcc-13-20250911/gcc/testsuite/gcc.target/i386/pieces-memcpy-21.c	Thu Sep 11 22:32:21 2025
--- gcc-13-20250918/gcc/testsuite/gcc.target/i386/pieces-memcpy-21.c	Thu Sep 18 22:32:53 2025
***************
*** 1,5 ****
  /* { dg-do compile } */
! /* { dg-options "-O2 -mtune=sapphirerapids -march=x86-64 -mavx2" } */
  
  extern char *dst, *src;
  
--- 1,5 ----
  /* { dg-do compile } */
! /* { dg-options "-O2 -mtune=znver5 -march=x86-64 -mavx2" } */
  
  extern char *dst, *src;
  
diff -Nrcpad gcc-13-20250911/gcc/testsuite/gcc.target/i386/pieces-memset-46.c gcc-13-20250918/gcc/testsuite/gcc.target/i386/pieces-memset-46.c
*** gcc-13-20250911/gcc/testsuite/gcc.target/i386/pieces-memset-46.c	Thu Sep 11 22:32:21 2025
--- gcc-13-20250918/gcc/testsuite/gcc.target/i386/pieces-memset-46.c	Thu Sep 18 22:32:53 2025
***************
*** 1,5 ****
  /* { dg-do compile } */
! /* { dg-options "-O2 -march=sapphirerapids" } */
  
  extern char *dst;
  
--- 1,5 ----
  /* { dg-do compile } */
! /* { dg-options "-O2 -march=znver5" } */
  
  extern char *dst;
  
diff -Nrcpad gcc-13-20250911/gcc/testsuite/gcc.target/i386/pieces-memset-49.c gcc-13-20250918/gcc/testsuite/gcc.target/i386/pieces-memset-49.c
*** gcc-13-20250911/gcc/testsuite/gcc.target/i386/pieces-memset-49.c	Thu Sep 11 22:32:21 2025
--- gcc-13-20250918/gcc/testsuite/gcc.target/i386/pieces-memset-49.c	Thu Sep 18 22:32:53 2025
***************
*** 1,5 ****
  /* { dg-do compile } */
! /* { dg-options "-O2 -mtune=sapphirerapids -march=x86-64 -mavx2" } */
  
  extern char *dst;
  
--- 1,5 ----
  /* { dg-do compile } */
! /* { dg-options "-O2 -mtune=znver5 -march=x86-64 -mavx2" } */
  
  extern char *dst;
  
diff -Nrcpad gcc-13-20250911/gcc/tree-sra.cc gcc-13-20250918/gcc/tree-sra.cc
*** gcc-13-20250911/gcc/tree-sra.cc	Thu Sep 11 22:32:31 2025
--- gcc-13-20250918/gcc/tree-sra.cc	Thu Sep 18 22:33:14 2025
*************** sort_and_splice_var_accesses (tree var)
*** 2302,2307 ****
--- 2302,2313 ----
  		}
  	      unscalarizable_region = true;
  	    }
+ 	  /* If there the same place is accessed with two incompatible
+ 	     aggregate types, trying to base total scalarization on either of
+ 	     them can be wrong.  */
+ 	  if (!first_scalar && !types_compatible_p (access->type, ac2->type))
+ 	    bitmap_set_bit (cannot_scalarize_away_bitmap,
+ 			    DECL_UID (access->base));
  
  	  if (grp_same_access_path
  	      && (!ac2->grp_same_access_path
*************** analyze_access_subtree (struct access *r
*** 2687,2693 ****
  
    for (child = root->first_child; child; child = child->next_sibling)
      {
!       hole |= covered_to < child->offset;
        sth_created |= analyze_access_subtree (child, root,
  					     allow_replacements && !scalar,
  					     totally);
--- 2693,2702 ----
  
    for (child = root->first_child; child; child = child->next_sibling)
      {
!       if (totally)
! 	covered_to = child->offset;
!       else
! 	hole |= covered_to < child->offset;
        sth_created |= analyze_access_subtree (child, root,
  					     allow_replacements && !scalar,
  					     totally);
*************** analyze_access_subtree (struct access *r
*** 2697,2702 ****
--- 2706,2713 ----
  	covered_to += child->size;
        else
  	hole = true;
+       if (totally && !hole)
+ 	covered_to = limit;
      }
  
    if (allow_replacements && scalar && !root->first_child
*************** analyze_access_subtree (struct access *r
*** 2765,2771 ****
  	root->grp_total_scalarization = 0;
      }
  
!   if (!hole || totally)
      root->grp_covered = 1;
    else if (root->grp_write || comes_initialized_p (root->base))
      root->grp_unscalarized_data = 1; /* not covered and written to */
--- 2776,2782 ----
  	root->grp_total_scalarization = 0;
      }
  
!   if (!hole)
      root->grp_covered = 1;
    else if (root->grp_write || comes_initialized_p (root->base))
      root->grp_unscalarized_data = 1; /* not covered and written to */
