diff -Nrcpad gcc-14-20250725/LAST_UPDATED gcc-14-20250801/LAST_UPDATED
*** gcc-14-20250725/LAST_UPDATED	Fri Jul 25 22:33:36 2025
--- gcc-14-20250801/LAST_UPDATED	Fri Aug  1 22:34:23 2025
***************
*** 1 ****
! Obtained from git: releases/gcc-14 revision 8be9bec735ad39e4cebacb31401b3707b0d0732f
--- 1 ----
! Obtained from git: releases/gcc-14 revision 000138675af3e1ee587b0fa17709ea62590860cb
diff -Nrcpad gcc-14-20250725/MD5SUMS gcc-14-20250801/MD5SUMS
*** gcc-14-20250725/MD5SUMS	Fri Jul 25 22:33:41 2025
--- gcc-14-20250801/MD5SUMS	Fri Aug  1 22:34:27 2025
***************
*** 1,5 ****
  # This file contains the MD5 checksums of the files in the
! # gcc-14-20250725.tar.xz tarball.
  #
  # Besides verifying that all files in the tarball were correctly expanded,
  # it also can be used to determine if any files have changed since the
--- 1,5 ----
  # This file contains the MD5 checksums of the files in the
! # gcc-14-20250801.tar.xz tarball.
  #
  # Besides verifying that all files in the tarball were correctly expanded,
  # it also can be used to determine if any files have changed since the
*************** fc9280b02bc68e4fb1ef8d51ccc25061  Change
*** 23,29 ****
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--- 23,29 ----
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*** 505,511 ****
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--- 505,511 ----
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*************** fb3fadb88e1d2b3b640cfaaa5ff11780  gcc/Ch
*** 541,547 ****
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--- 541,547 ----
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*************** d9397260c45e57a1d9da554ae2e2a646  gcc/co
*** 3347,3353 ****
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--- 3347,3353 ----
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*************** d3d0a9db4cb45433208c51520e54f3bb  gcc/co
*** 3364,3376 ****
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--- 3364,3376 ----
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*************** d0eb4ba200acb78424e4f81fef87ed74  gcc/co
*** 3395,3401 ****
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--- 3395,3401 ----
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*************** fccc6d65638a2ce66ebc6b06766912c2  gcc/co
*** 4065,4071 ****
  4f7ab8c57b3148a31d24838528313ef2  gcc/config/i386/i386-rust.h
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--- 4065,4071 ----
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*************** e82f2dd2df5fd204d1c7102be6f29c11  gcc/co
*** 4132,4138 ****
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--- 4132,4138 ----
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*************** ba884745a15d4b194d0ad2e286b0c617  gcc/co
*** 4284,4290 ****
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--- 4284,4290 ----
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*************** ea6cc43b3fa3313db4228947eed2152e  gcc/co
*** 4307,4318 ****
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--- 4307,4318 ----
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*************** d36a2aabdf8da39363d9be0efef739b0  gcc/co
*** 5361,5367 ****
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--- 5361,5367 ----
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*************** eb0e2e62caf98260cc2641216d140ae9  gcc/cp
*** 5401,5407 ****
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--- 5401,5407 ----
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*************** e8a9eb01b9451a357155e7152df1c669  gcc/ta
*** 8060,8066 ****
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--- 8060,8066 ----
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*************** f4f262de9adf968192a3da56a3c4adc1  gcc/te
*** 15499,15504 ****
--- 15499,15505 ----
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  8b7c8e7c1b64cfa0626f7f2311c9fef5  gcc/testsuite/g++.dg/cpp0x/constexpr-array3.C
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  be6358dd3b71be0a5561e5437089998e  gcc/testsuite/g++.dg/cpp0x/constexpr-array6.C
*************** c0b015cd02e07242444c2700f64e070a  gcc/te
*** 20257,20262 ****
--- 20258,20264 ----
  5fd97c22b2996faaa87a3aa20de08243  gcc/testsuite/g++.dg/cpp2a/constexpr-union6.C
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  e94cea4fa4255420603d88768e70b36c  gcc/testsuite/g++.dg/cpp2a/constexpr-union8.C
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*************** afe62fa89b5483576738572de037298b  gcc/te
*** 59152,59160 ****
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! eb580446b9c202515566ebe3c407f886  gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_1.c
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--- 59154,59162 ----
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! 20f0fd449cd7c00774afe0e41e6b997a  gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_1.c
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! d97792582b32991bd0603548569a5a10  gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_11.c
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*************** df9a1b5d24aec3bc8a0ef502ec0a64b9  gcc/te
*** 59198,59203 ****
--- 59200,59206 ----
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  cea477cbfc0138870da19d13a6f78a5c  gcc/testsuite/gcc.target/aarch64/sme/nonlocal_goto_7.c
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*************** ae44d68f203e7d5a17d19738cfbc53a0  gcc/te
*** 62039,62044 ****
--- 62042,62048 ----
  23037c19fa0b1b3f5bcac32c8d73393c  gcc/testsuite/gcc.target/aarch64/sve/acle/general/nrv_1.c
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*************** f247489d5a83c25a52bba3f69ccf6256  gcc/te
*** 62783,62788 ****
--- 62787,62793 ----
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*************** eea712e5edcebcf47419b6442fd41bd4  gcc/te
*** 73722,73728 ****
  b72099cd966e9c576a224799821d5d28  gcc/testsuite/gcc.target/i386/cold-attribute-1.c
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! dcc5b76590328fd9f7c421fcb66d52d6  gcc/testsuite/gcc.target/i386/cold-attribute-4.c
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--- 73727,73733 ----
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! fb80b8e91abc0725f03bd2c87f0692c9  gcc/testsuite/gcc.target/i386/cold-attribute-4.c
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*************** ef2cdb48cbe0dedfce0d7eb770a1f30f  gcc/te
*** 75200,75207 ****
--- 75205,75218 ----
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*************** b4671c279162dd2c1fd844929bdbbc6b  gcc/te
*** 78413,78418 ****
--- 78424,78430 ----
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  dfa82d46bae04856dd91309f03684574  gcc/testsuite/gcc.target/loongarch/recip-sqrtf.c
*************** d128b18a20f2a55978e519508f48f1ae  gcc/te
*** 82555,82561 ****
  cdde8569ebb2ca104f942dd183c12fa2  gcc/testsuite/gcc.target/powerpc/vsx-builtin-4.c
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! b85a4370874d0558ca845f7c6e5f0a6d  gcc/testsuite/gcc.target/powerpc/vsx-builtin-7.c
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--- 82567,82573 ----
  cdde8569ebb2ca104f942dd183c12fa2  gcc/testsuite/gcc.target/powerpc/vsx-builtin-4.c
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! a3ba74a674fd49b3c22b51c6c608e158  gcc/testsuite/gcc.target/powerpc/vsx-builtin-7.c
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  2e9c4b2355be46611bfe42e4a9f8d1f3  gcc/testsuite/gcc.target/powerpc/vsx-builtin-9b.c
*************** b007b2d97ecc0ea9c1d6d6f84e9ebbeb  gcc/tr
*** 110387,110393 ****
  43f6f3fee20eb715fd451bf19e9bfd4c  gcc/tree-vect-patterns.cc
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  62afed2a3920f38b0d29565df04b36c8  gcc/tree-vect-slp.cc
! 7087e1001e8da317b21b1581d837a86c  gcc/tree-vect-stmts.cc
  795c5280c71f566f4b3e8c7fdcc3b609  gcc/tree-vector-builder.cc
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--- 110399,110405 ----
  43f6f3fee20eb715fd451bf19e9bfd4c  gcc/tree-vect-patterns.cc
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! 94b9d0473f1224b15afac8c692bc869e  gcc/tree-vect-stmts.cc
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  250ce9e7ca93bb776afda377af2c190d  gcc/tree-vector-builder.h
  c5a03f7f18d4c4b5f0a74529e044ddfe  gcc/tree-vectorizer.cc
*************** e0bd9b8669e44ec6010f92da1d5188ad  libqua
*** 123107,123113 ****
  af84fa5118f4adec8393614994e1c4d6  libquadmath/strtod/strtoflt128.c
  d15a18f7c46ba2add6148edc5b7563c0  libquadmath/strtod/tens_in_limb.c
  12c73a846f7668d29de720bd79502bef  libquadmath/update-quadmath.py
! f7cc0c2fc27f790ab3c616f5a12dcec3  libsanitizer/ChangeLog
  63916ba64a3cfa7ce2809fb46ab38597  libsanitizer/HOWTO_MERGE
  0249c37748936faf5b1efd5789587909  libsanitizer/LICENSE.TXT
  894b596d6d81ab8f2fb0708e8bc83e83  libsanitizer/LOCAL_PATCHES
--- 123119,123125 ----
  af84fa5118f4adec8393614994e1c4d6  libquadmath/strtod/strtoflt128.c
  d15a18f7c46ba2add6148edc5b7563c0  libquadmath/strtod/tens_in_limb.c
  12c73a846f7668d29de720bd79502bef  libquadmath/update-quadmath.py
! 78704e57c6c65b612343ff7c68143284  libsanitizer/ChangeLog
  63916ba64a3cfa7ce2809fb46ab38597  libsanitizer/HOWTO_MERGE
  0249c37748936faf5b1efd5789587909  libsanitizer/LICENSE.TXT
  894b596d6d81ab8f2fb0708e8bc83e83  libsanitizer/LOCAL_PATCHES
*************** a32b38d2eae806bfe95f3e089a711f7a  libsan
*** 123330,123336 ****
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  0a68626fb68e0f53b782fec8d795f632  libsanitizer/sanitizer_common/sanitizer_common_interceptors_format.inc
! aa961fb0d47d9369601c5aa4bd24ea02  libsanitizer/sanitizer_common/sanitizer_common_interceptors_ioctl.inc
  92d324a2c8f8e44cf13d5f7c545d6c1d  libsanitizer/sanitizer_common/sanitizer_common_interceptors_memintrinsics.inc
  c664d5fb1514c978d28a6a62b2040b53  libsanitizer/sanitizer_common/sanitizer_common_interceptors_netbsd_compat.inc
  e19e7b0a6d9409a4b3a5c277ebba0b9a  libsanitizer/sanitizer_common/sanitizer_common_interceptors_vfork_aarch64.inc.S
--- 123342,123348 ----
  8d31e033038441d83d7dac7241fa7288  libsanitizer/sanitizer_common/sanitizer_common.h
  0efb1be2c27a1a3b31edbde3b5472fc4  libsanitizer/sanitizer_common/sanitizer_common_interceptors.inc
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! f7ca723d15d4d448c700727f05b86537  libsanitizer/sanitizer_common/sanitizer_common_interceptors_ioctl.inc
  92d324a2c8f8e44cf13d5f7c545d6c1d  libsanitizer/sanitizer_common/sanitizer_common_interceptors_memintrinsics.inc
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  e19e7b0a6d9409a4b3a5c277ebba0b9a  libsanitizer/sanitizer_common/sanitizer_common_interceptors_vfork_aarch64.inc.S
*************** a4d7b3990585330fb0fbc99e5afaf019  libsan
*** 123411,123418 ****
  0865bdc585846a1c9cfa5d1df0517d02  libsanitizer/sanitizer_common/sanitizer_platform_limits_netbsd.h
  d41d8cd98f00b204e9800998ecf8427e  libsanitizer/sanitizer_common/sanitizer_platform_limits_openbsd.cpp
  d41d8cd98f00b204e9800998ecf8427e  libsanitizer/sanitizer_common/sanitizer_platform_limits_openbsd.h
! de3519edf4a524cdab4336d4eeed94e0  libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.cpp
! 1c6ecd7b7fd7b299a11f160ad0de1043  libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h
  711b54008ada7faff939a95e325b185b  libsanitizer/sanitizer_common/sanitizer_platform_limits_solaris.cpp
  ab1ad414331f77e459da9a32b756cbac  libsanitizer/sanitizer_common/sanitizer_platform_limits_solaris.h
  e3606cc19e7b02bfba7878ba5d6ce75a  libsanitizer/sanitizer_common/sanitizer_posix.cpp
--- 123423,123430 ----
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  d41d8cd98f00b204e9800998ecf8427e  libsanitizer/sanitizer_common/sanitizer_platform_limits_openbsd.h
! 5f00dd4cf135e46663fd6d3b724b06c1  libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.cpp
! 621396f7d74ae5075a70cd01f5daac83  libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h
  711b54008ada7faff939a95e325b185b  libsanitizer/sanitizer_common/sanitizer_platform_limits_solaris.cpp
  ab1ad414331f77e459da9a32b756cbac  libsanitizer/sanitizer_common/sanitizer_platform_limits_solaris.h
  e3606cc19e7b02bfba7878ba5d6ce75a  libsanitizer/sanitizer_common/sanitizer_posix.cpp
diff -Nrcpad gcc-14-20250725/gcc/ChangeLog gcc-14-20250801/gcc/ChangeLog
*** gcc-14-20250725/gcc/ChangeLog	Fri Jul 25 22:32:10 2025
--- gcc-14-20250801/gcc/ChangeLog	Fri Aug  1 22:32:36 2025
***************
*** 1,3 ****
--- 1,106 ----
+ 2025-07-31  Spencer Abson  <spencer.abson@arm.com>
+ 
+ 	Backported from master:
+ 	2025-07-31  Spencer Abson  <spencer.abson@arm.com>
+ 
+ 	PR target/121028
+ 	* config/aarch64/aarch64-sme.md (aarch64_smstart_sm): Use the .inst
+ 	directive if !TARGET_SME.
+ 	(aarch64_smstop_sm): Likewise.
+ 
+ 2025-07-31  H.J. Lu  <hjl.tools@gmail.com>
+ 
+ 	Backported from master:
+ 	2025-07-30  H.J. Lu  <hjl.tools@gmail.com>
+ 
+ 	PR target/120427
+ 	* config/i386/i386.md (peephole2): Transform "movq $-1,reg" to
+ 	"pushq $-1; popq reg" for -Oz if reg is a legacy integer register.
+ 
+ 2025-07-31  liuhongt  <hongtao.liu@intel.com>
+ 
+ 	Backported from master:
+ 	2025-07-30  liuhongt  <hongtao.liu@intel.com>
+ 
+ 	PR target/121274
+ 	* config/i386/sse.md (*vec_concatv2di_0): Add a splitter
+ 	before it.
+ 
+ 2025-07-29  H.J. Lu  <hjl.tools@gmail.com>
+ 
+ 	Backported from master:
+ 	2025-06-19  H.J. Lu  <hjl.tools@gmail.com>
+ 
+ 	PR target/120427
+ 	* config/i386/i386.md (*mov<mode>_and): Changed to
+ 	define_insn_and_split.  Split it to "mov $0,mem" if not -Oz.
+ 	(*mov<mode>_or): Changed to define_insn_and_split.  Split it
+ 	to "mov $-1,mem" if not -Oz.
+ 	(peephole2): Don't transform "mov $-1,reg" to "push $-1; pop reg"
+ 	for -Oz since it will be transformed to "or $-1,reg".
+ 
+ 2025-07-28  Xi Ruoyao  <xry111@xry111.site>
+ 
+ 	Backported from master:
+ 	2025-07-17  Xi Ruoyao  <xry111@xry111.site>
+ 
+ 	PR target/121064
+ 	* config/loongarch/lsx.md (lsx_vshuf_<lsxfmt_f>): Add '@' to
+ 	generate a mode-aware helper.  Use <VIMODE> as the mode of the
+ 	operand 1 (selector).
+ 	* config/loongarch/lasx.md (lasx_xvshuf_<lasxfmt_f>): Likewise.
+ 	* config/loongarch/loongarch.cc
+ 	(loongarch_try_expand_lsx_vshuf_const): Create a new pseudo for
+ 	the selector.  Use the mode-aware helper to simplify the code.
+ 	(loongarch_expand_vec_perm_const): Likewise.
+ 
+ 2025-07-26  Richard Sandiford  <richard.sandiford@arm.com>
+ 
+ 	Backported from master:
+ 	2025-07-11  Richard Sandiford  <richard.sandiford@arm.com>
+ 
+ 	PR target/121027
+ 	* config/aarch64/aarch64.cc (aarch64_evpc_sve_tbl): Punt on 2-input
+ 	operations that can be handled by vec_perm.
+ 
+ 2025-07-26  Richard Sandiford  <richard.sandiford@arm.com>
+ 
+ 	Backported from master:
+ 	2024-10-07  Richard Sandiford  <richard.sandiford@arm.com>
+ 
+ 	PR target/121027
+ 	* config/aarch64/iterators.md (SVE_I): Move further up file.
+ 	(SVE_F): New mode iterator.
+ 	(SVE_ALL): Redefine in terms of SVE_I and SVE_F.
+ 	* config/aarch64/aarch64-sve.md (*<LOGICALF:optab><mode>3): Extend
+ 	to all SVE_F.
+ 
+ 2025-07-26  Richard Sandiford  <richard.sandiford@arm.com>
+ 
+ 	Backported from master:
+ 	2025-07-07  Richard Sandiford  <richard.sandiford@arm.com>
+ 
+ 	PR target/118891
+ 	* config/aarch64/aarch64.cc (aarch64_expand_vector_init): Fix the
+ 	ZIP1 operand order for big-endian targets.
+ 
+ 2025-07-26  Richard Sandiford  <richard.sandiford@arm.com>
+ 
+ 	Backported from master:
+ 	2025-07-07  Richard Sandiford  <richard.sandiford@arm.com>
+ 
+ 	* config/aarch64/aarch64-sve.md (@aarch64_sve_set_neonq_<mode>):
+ 	Use %Z instead of lowpart_subreg.  Tweak formatting.
+ 
+ 2025-07-26  Richard Sandiford  <richard.sandiford@arm.com>
+ 
+ 	Backported from master:
+ 	2025-07-07  Richard Sandiford  <richard.sandiford@arm.com>
+ 
+ 	PR tree-optimization/118891
+ 	* tree-vect-stmts.cc (supportable_widening_operation): Swap the
+ 	hi and lo internal functions on big-endian targets.
+ 
  2025-07-22  Haochen Gui  <guihaoc@gcc.gnu.org>
  
  	Backported from master:
diff -Nrcpad gcc-14-20250725/gcc/DATESTAMP gcc-14-20250801/gcc/DATESTAMP
*** gcc-14-20250725/gcc/DATESTAMP	Fri Jul 25 22:32:10 2025
--- gcc-14-20250801/gcc/DATESTAMP	Fri Aug  1 22:32:37 2025
***************
*** 1 ****
! 20250725
--- 1 ----
! 20250801
diff -Nrcpad gcc-14-20250725/gcc/config/aarch64/aarch64-sme.md gcc-14-20250801/gcc/config/aarch64/aarch64-sme.md
*** gcc-14-20250725/gcc/config/aarch64/aarch64-sme.md	Fri Jul 25 22:32:12 2025
--- gcc-14-20250801/gcc/config/aarch64/aarch64-sme.md	Fri Aug  1 22:32:38 2025
***************
*** 61,66 ****
--- 61,70 ----
  ;; (b) they are sometimes used conditionally, particularly in streaming-
  ;; compatible code.
  ;;
+ ;; To prevent the latter from upsetting the assembler, we emit the literal
+ ;; encodings of "SMSTART SM" and "SMSTOP SM" when compiling without
+ ;; TARGET_SME.
+ ;;
  ;; =========================================================================
  
  ;; -------------------------------------------------------------------------
***************
*** 160,166 ****
     (clobber (reg:VNx16BI P14_REGNUM))
     (clobber (reg:VNx16BI P15_REGNUM))]
    ""
!   "smstart\tsm"
  )
  
  ;; Turn off streaming mode.  This clobbers all SVE state.
--- 164,172 ----
     (clobber (reg:VNx16BI P14_REGNUM))
     (clobber (reg:VNx16BI P15_REGNUM))]
    ""
!   {
!     return TARGET_SME ? "smstart\tsm" : ".inst 0xd503437f // smstart sm";
!   }
  )
  
  ;; Turn off streaming mode.  This clobbers all SVE state.
***************
*** 195,201 ****
     (clobber (reg:VNx16BI P14_REGNUM))
     (clobber (reg:VNx16BI P15_REGNUM))]
    ""
!   "smstop\tsm"
  )
  
  ;; -------------------------------------------------------------------------
--- 201,209 ----
     (clobber (reg:VNx16BI P14_REGNUM))
     (clobber (reg:VNx16BI P15_REGNUM))]
    ""
!   {
!     return TARGET_SME ? "smstop\tsm" : ".inst 0xd503427f // smstop sm";
!   }
  )
  
  ;; -------------------------------------------------------------------------
diff -Nrcpad gcc-14-20250725/gcc/config/aarch64/aarch64-sve.md gcc-14-20250801/gcc/config/aarch64/aarch64-sve.md
*** gcc-14-20250725/gcc/config/aarch64/aarch64-sve.md	Fri Jul 25 22:32:12 2025
--- gcc-14-20250801/gcc/config/aarch64/aarch64-sve.md	Fri Aug  1 22:32:38 2025
***************
*** 6422,6431 ****
  ;; by providing this, but we need to use UNSPECs since rtx logical ops
  ;; aren't defined for floating-point modes.
  (define_insn "*<optab><mode>3"
!   [(set (match_operand:SVE_FULL_F 0 "register_operand" "=w")
! 	(unspec:SVE_FULL_F
! 	  [(match_operand:SVE_FULL_F 1 "register_operand" "w")
! 	   (match_operand:SVE_FULL_F 2 "register_operand" "w")]
  	  LOGICALF))]
    "TARGET_SVE"
    "<logicalf_op>\t%0.d, %1.d, %2.d"
--- 6422,6431 ----
  ;; by providing this, but we need to use UNSPECs since rtx logical ops
  ;; aren't defined for floating-point modes.
  (define_insn "*<optab><mode>3"
!   [(set (match_operand:SVE_F 0 "register_operand" "=w")
! 	(unspec:SVE_F
! 	  [(match_operand:SVE_F 1 "register_operand" "w")
! 	   (match_operand:SVE_F 2 "register_operand" "w")]
  	  LOGICALF))]
    "TARGET_SVE"
    "<logicalf_op>\t%0.d, %1.d, %2.d"
***************
*** 10989,11004 ****
  
  (define_insn "@aarch64_sve_set_neonq_<mode>"
    [(set (match_operand:SVE_FULL 0 "register_operand" "=w")
!       (unspec:SVE_FULL
! 	[(match_operand:SVE_FULL 1 "register_operand" "w")
! 	(match_operand:<V128> 2 "register_operand" "w")
! 	(match_operand:<VPRED> 3 "register_operand" "Upl")]
! 	UNSPEC_SET_NEONQ))]
    "TARGET_SVE
     && BYTES_BIG_ENDIAN"
!   {
!     operands[2] = lowpart_subreg (<MODE>mode, operands[2],
!                                   GET_MODE (operands[2]));
!     return "sel\t%0.<Vetype>, %3, %2.<Vetype>, %1.<Vetype>";
!   }
  )
--- 10989,11000 ----
  
  (define_insn "@aarch64_sve_set_neonq_<mode>"
    [(set (match_operand:SVE_FULL 0 "register_operand" "=w")
! 	(unspec:SVE_FULL
! 	  [(match_operand:SVE_FULL 1 "register_operand" "w")
! 	   (match_operand:<V128> 2 "register_operand" "w")
! 	   (match_operand:<VPRED> 3 "register_operand" "Upl")]
! 	  UNSPEC_SET_NEONQ))]
    "TARGET_SVE
     && BYTES_BIG_ENDIAN"
!   "sel\t%0.<Vetype>, %3, %Z2.<Vetype>, %1.<Vetype>"
  )
diff -Nrcpad gcc-14-20250725/gcc/config/aarch64/aarch64.cc gcc-14-20250801/gcc/config/aarch64/aarch64.cc
*** gcc-14-20250725/gcc/config/aarch64/aarch64.cc	Fri Jul 25 22:32:12 2025
--- gcc-14-20250801/gcc/config/aarch64/aarch64.cc	Fri Aug  1 22:32:38 2025
*************** aarch64_expand_vector_init (rtx target,
*** 24019,24024 ****
--- 24019,24031 ----
        emit_insn (rec_seq);
      }
  
+   /* The two halves should (by induction) be individually endian-correct.
+      However, in the memory layout provided by VALS, the nth element of
+      HALVES[0] comes immediately before the nth element HALVES[1].
+      This means that, on big-endian targets, the nth element of HALVES[0]
+      is more significant than the nth element HALVES[1].  */
+   if (BYTES_BIG_ENDIAN)
+     std::swap (halves[0], halves[1]);
    rtvec v = gen_rtvec (2, halves[0], halves[1]);
    rtx_insn *zip1_insn
      = emit_set_insn (target, gen_rtx_UNSPEC (mode, v, UNSPEC_ZIP1));
*************** aarch64_evpc_tbl (struct expand_vec_perm
*** 25934,25945 ****
  static bool
  aarch64_evpc_sve_tbl (struct expand_vec_perm_d *d)
  {
!   unsigned HOST_WIDE_INT nelt;
  
!   /* Permuting two variable-length vectors could overflow the
!      index range.  */
!   if (!d->one_vector_p && !d->perm.length ().is_constant (&nelt))
!     return false;
  
    if (d->testing_p)
      return true;
--- 25941,25963 ----
  static bool
  aarch64_evpc_sve_tbl (struct expand_vec_perm_d *d)
  {
!   if (!d->one_vector_p)
!     {
!       /* aarch64_expand_sve_vec_perm does not yet handle variable-length
! 	 vectors.  */
!       if (!d->perm.length ().is_constant ())
! 	return false;
  
!       /* This permutation reduces to the vec_perm optab if the elements are
! 	 large enough to hold all selector indices.  Do not handle that case
! 	 here, since the general TBL+SUB+TBL+ORR sequence is too expensive to
! 	 be considered a "native" constant permutation.
! 
! 	 Not doing this would undermine code that queries can_vec_perm_const_p
! 	 with allow_variable_p set to false.  See PR121027.  */
!       if (selector_fits_mode_p (d->vmode, d->perm))
! 	return false;
!     }
  
    if (d->testing_p)
      return true;
diff -Nrcpad gcc-14-20250725/gcc/config/aarch64/iterators.md gcc-14-20250801/gcc/config/aarch64/iterators.md
*** gcc-14-20250725/gcc/config/aarch64/iterators.md	Fri Jul 25 22:32:12 2025
--- gcc-14-20250801/gcc/config/aarch64/iterators.md	Fri Aug  1 22:32:38 2025
***************
*** 519,533 ****
  				     VNx4HI VNx2HI
  				     VNx2SI])
  
  ;; All SVE vector modes.
! (define_mode_iterator SVE_ALL [VNx16QI VNx8QI VNx4QI VNx2QI
! 			       VNx8HI VNx4HI VNx2HI
! 			       VNx8HF VNx4HF VNx2HF
! 			       VNx8BF VNx4BF VNx2BF
! 			       VNx4SI VNx2SI
! 			       VNx4SF VNx2SF
! 			       VNx2DI
! 			       VNx2DF])
  
  ;; All SVE 2-vector modes.
  (define_mode_iterator SVE_FULLx2 [VNx32QI VNx16HI VNx8SI VNx4DI
--- 519,538 ----
  				     VNx4HI VNx2HI
  				     VNx2SI])
  
+ ;; All SVE integer vector modes.
+ (define_mode_iterator SVE_I [VNx16QI VNx8QI VNx4QI VNx2QI
+ 			     VNx8HI VNx4HI VNx2HI
+ 			     VNx4SI VNx2SI
+ 			     VNx2DI])
+ 
+ ;; All SVE floating-point vector modes.
+ (define_mode_iterator SVE_F [VNx8HF VNx4HF VNx2HF
+ 			     VNx8BF VNx4BF VNx2BF
+ 			     VNx4SF VNx2SF
+ 			     VNx2DF])
+ 
  ;; All SVE vector modes.
! (define_mode_iterator SVE_ALL [SVE_I SVE_F])
  
  ;; All SVE 2-vector modes.
  (define_mode_iterator SVE_FULLx2 [VNx32QI VNx16HI VNx8SI VNx4DI
***************
*** 549,560 ****
  ;; All SVE vector and structure modes.
  (define_mode_iterator SVE_ALL_STRUCT [SVE_ALL SVE_STRUCT])
  
- ;; All SVE integer vector modes.
- (define_mode_iterator SVE_I [VNx16QI VNx8QI VNx4QI VNx2QI
- 			     VNx8HI VNx4HI VNx2HI
- 			     VNx4SI VNx2SI
- 			     VNx2DI])
- 
  ;; All SVE integer vector modes and Advanced SIMD 64-bit vector
  ;; element modes
  (define_mode_iterator SVE_I_SIMD_DI [SVE_I V2DI])
--- 554,559 ----
diff -Nrcpad gcc-14-20250725/gcc/config/i386/i386.md gcc-14-20250801/gcc/config/i386/i386.md
*** gcc-14-20250725/gcc/config/i386/i386.md	Fri Jul 25 22:32:12 2025
--- gcc-14-20250801/gcc/config/i386/i386.md	Fri Aug  1 22:32:38 2025
***************
*** 2332,2353 ****
     (set_attr "mode" "SI")
     (set_attr "length_immediate" "0")])
  
! (define_insn "*mov<mode>_and"
    [(set (match_operand:SWI248 0 "memory_operand" "=m")
  	(match_operand:SWI248 1 "const0_operand"))
     (clobber (reg:CC FLAGS_REG))]
    "reload_completed"
    "and{<imodesuffix>}\t{%1, %0|%0, %1}"
    [(set_attr "type" "alu1")
     (set_attr "mode" "<MODE>")
     (set_attr "length_immediate" "1")])
  
! (define_insn "*mov<mode>_or"
    [(set (match_operand:SWI248 0 "nonimmediate_operand" "=rm")
  	(match_operand:SWI248 1 "constm1_operand"))
     (clobber (reg:CC FLAGS_REG))]
    "reload_completed"
    "or{<imodesuffix>}\t{%1, %0|%0, %1}"
    [(set_attr "type" "alu1")
     (set_attr "mode" "<MODE>")
     (set_attr "length_immediate" "1")])
--- 2332,2363 ----
     (set_attr "mode" "SI")
     (set_attr "length_immediate" "0")])
  
! ;; Generate shorter "and $0,mem" for -Oz.  Split it to "mov $0,mem"
! ;; otherwise.
! (define_insn_and_split "*mov<mode>_and"
    [(set (match_operand:SWI248 0 "memory_operand" "=m")
  	(match_operand:SWI248 1 "const0_operand"))
     (clobber (reg:CC FLAGS_REG))]
    "reload_completed"
    "and{<imodesuffix>}\t{%1, %0|%0, %1}"
+   "&& !(optimize_insn_for_size_p () && optimize_size > 1)"
+   [(set (match_dup 0) (match_dup 1))]
+   ""
    [(set_attr "type" "alu1")
     (set_attr "mode" "<MODE>")
     (set_attr "length_immediate" "1")])
  
! ;; Generate shorter "or $-1,mem" for -Oz.  Split it to "mov $-1,mem"
! ;; otherwise.
! (define_insn_and_split "*mov<mode>_or"
    [(set (match_operand:SWI248 0 "nonimmediate_operand" "=rm")
  	(match_operand:SWI248 1 "constm1_operand"))
     (clobber (reg:CC FLAGS_REG))]
    "reload_completed"
    "or{<imodesuffix>}\t{%1, %0|%0, %1}"
+   "&& !(optimize_insn_for_size_p () && optimize_size > 1)"
+   [(set (match_dup 0) (match_dup 1))]
+   ""
    [(set_attr "type" "alu1")
     (set_attr "mode" "<MODE>")
     (set_attr "length_immediate" "1")])
***************
*** 2852,2857 ****
--- 2862,2869 ----
  	(match_operand:SWI248 1 "const_int_operand"))]
    "optimize_insn_for_size_p () && optimize_size > 1
     && operands[1] != const0_rtx
+    && (operands[1] != constm1_rtx
+        || (<MODE>mode == DImode && LEGACY_INT_REG_P (operands[0])))
     && IN_RANGE (INTVAL (operands[1]), -128, 127)
     && !ix86_red_zone_used
     && REGNO (operands[0]) != SP_REG"
diff -Nrcpad gcc-14-20250725/gcc/config/i386/sse.md gcc-14-20250801/gcc/config/i386/sse.md
*** gcc-14-20250725/gcc/config/i386/sse.md	Fri Jul 25 22:32:12 2025
--- gcc-14-20250801/gcc/config/i386/sse.md	Fri Aug  1 22:32:38 2025
***************
*** 20793,20798 ****
--- 20793,20811 ----
  	   (const_string "orig")))
     (set_attr "mode" "TI,TI,TI,TI,TI,TI,V4SF,V2SF,V2SF")])
  
+ ;; Eliminate redundancy caused by
+ ;; /* Special case TImode to 128-bit vector conversions via V2DI.  */
+ ;; in ix86_expand_vector_move
+ 
+ (define_split
+   [(set (match_operand:V2DI 0 "register_operand")
+ 	(vec_concat:V2DI
+ 	  (subreg:DI (match_operand:TI 1 "register_operand") 0)
+ 	  (subreg:DI (match_dup 1) 8)))]
+   "TARGET_SSE2 && ix86_pre_reload_split ()"
+   [(set (match_dup 0)
+ 	(subreg:V2DI (match_dup 1) 0))])
+ 
  (define_insn "*vec_concatv2di_0"
    [(set (match_operand:V2DI 0 "register_operand"     "=v,v ,x")
  	(vec_concat:V2DI
diff -Nrcpad gcc-14-20250725/gcc/config/loongarch/lasx.md gcc-14-20250801/gcc/config/loongarch/lasx.md
*** gcc-14-20250725/gcc/config/loongarch/lasx.md	Fri Jul 25 22:32:12 2025
--- gcc-14-20250801/gcc/config/loongarch/lasx.md	Fri Aug  1 22:32:40 2025
***************
*** 2337,2345 ****
    [(set_attr "type" "simd_int_arith")
     (set_attr "mode" "<MODE>")])
  
! (define_insn "lasx_xvshuf_<lasxfmt_f>"
    [(set (match_operand:LASX_DWH 0 "register_operand" "=f")
! 	(unspec:LASX_DWH [(match_operand:LASX_DWH 1 "register_operand" "0")
  			  (match_operand:LASX_DWH 2 "register_operand" "f")
  			  (match_operand:LASX_DWH 3 "register_operand" "f")]
  			UNSPEC_LASX_XVSHUF))]
--- 2337,2345 ----
    [(set_attr "type" "simd_int_arith")
     (set_attr "mode" "<MODE>")])
  
! (define_insn "@lasx_xvshuf_<lasxfmt_f>"
    [(set (match_operand:LASX_DWH 0 "register_operand" "=f")
! 	(unspec:LASX_DWH [(match_operand:<VIMODE> 1 "register_operand" "0")
  			  (match_operand:LASX_DWH 2 "register_operand" "f")
  			  (match_operand:LASX_DWH 3 "register_operand" "f")]
  			UNSPEC_LASX_XVSHUF))]
diff -Nrcpad gcc-14-20250725/gcc/config/loongarch/loongarch.cc gcc-14-20250801/gcc/config/loongarch/loongarch.cc
*** gcc-14-20250725/gcc/config/loongarch/loongarch.cc	Fri Jul 25 22:32:12 2025
--- gcc-14-20250801/gcc/config/loongarch/loongarch.cc	Fri Aug  1 22:32:40 2025
*************** static bool
*** 8199,8205 ****
  loongarch_try_expand_lsx_vshuf_const (struct expand_vec_perm_d *d)
  {
    int i;
!   rtx target, op0, op1, sel, tmp;
    rtx rperm[MAX_VECT_LEN];
  
    if (GET_MODE_SIZE (d->vmode) == 16)
--- 8199,8205 ----
  loongarch_try_expand_lsx_vshuf_const (struct expand_vec_perm_d *d)
  {
    int i;
!   rtx target, op0, op1;
    rtx rperm[MAX_VECT_LEN];
  
    if (GET_MODE_SIZE (d->vmode) == 16)
*************** loongarch_try_expand_lsx_vshuf_const (st
*** 8218,8264 ****
        for (i = 0; i < d->nelt; i += 1)
  	  rperm[i] = GEN_INT (d->perm[i]);
  
!       if (d->vmode == E_V2DFmode)
! 	{
! 	  sel = gen_rtx_CONST_VECTOR (E_V2DImode, gen_rtvec_v (d->nelt, rperm));
! 	  tmp = simplify_gen_subreg (E_V2DImode, d->target, d->vmode, 0);
! 	  emit_move_insn (tmp, sel);
! 	}
!       else if (d->vmode == E_V4SFmode)
! 	{
! 	  sel = gen_rtx_CONST_VECTOR (E_V4SImode, gen_rtvec_v (d->nelt, rperm));
! 	  tmp = simplify_gen_subreg (E_V4SImode, d->target, d->vmode, 0);
! 	  emit_move_insn (tmp, sel);
! 	}
!       else
! 	{
! 	  sel = gen_rtx_CONST_VECTOR (d->vmode, gen_rtvec_v (d->nelt, rperm));
! 	  emit_move_insn (d->target, sel);
! 	}
  
!       switch (d->vmode)
! 	{
! 	case E_V2DFmode:
! 	  emit_insn (gen_lsx_vshuf_d_f (target, target, op1, op0));
! 	  break;
! 	case E_V2DImode:
! 	  emit_insn (gen_lsx_vshuf_d (target, target, op1, op0));
! 	  break;
! 	case E_V4SFmode:
! 	  emit_insn (gen_lsx_vshuf_w_f (target, target, op1, op0));
! 	  break;
! 	case E_V4SImode:
! 	  emit_insn (gen_lsx_vshuf_w (target, target, op1, op0));
! 	  break;
! 	case E_V8HImode:
! 	  emit_insn (gen_lsx_vshuf_h (target, target, op1, op0));
! 	  break;
! 	case E_V16QImode:
! 	  emit_insn (gen_lsx_vshuf_b (target, op1, op0, target));
! 	  break;
! 	default:
! 	  break;
! 	}
  
        return true;
      }
--- 8218,8240 ----
        for (i = 0; i < d->nelt; i += 1)
  	  rperm[i] = GEN_INT (d->perm[i]);
  
!       machine_mode sel_mode = related_int_vector_mode (d->vmode)
! 	.require ();
!       rtvec sel_v = gen_rtvec_v (d->nelt, rperm);
  
!       /* Despite vshuf.* (except vshuf.b) needs sel == target, we cannot
! 	 load sel into target right now: here we are dealing with
! 	 pseudo regs, and target may be the same pseudo as one of op0
! 	 or op1.  Then we'd clobber the input.  Instead, we use a new
! 	 pseudo reg here.  The reload pass will look at the constraint
! 	 of vshuf.* and move sel into target first if needed.  */
!       rtx sel = force_reg (sel_mode,
! 			   gen_rtx_CONST_VECTOR (sel_mode, sel_v));
! 
!       if (d->vmode == E_V16QImode)
! 	emit_insn (gen_lsx_vshuf_b (target, op1, op0, sel));
!       else
! 	emit_insn (gen_lsx_vshuf (d->vmode, target, sel, op1, op0));
  
        return true;
      }
*************** loongarch_expand_vec_perm_const (struct
*** 9254,9260 ****
    bool flag = false;
    unsigned int i;
    unsigned char idx;
!   rtx target, op0, op1, sel, tmp;
    rtx rperm[MAX_VECT_LEN];
    unsigned int remapped[MAX_VECT_LEN];
    unsigned char perm2[MAX_VECT_LEN];
--- 9230,9236 ----
    bool flag = false;
    unsigned int i;
    unsigned char idx;
!   rtx target, op0, op1;
    rtx rperm[MAX_VECT_LEN];
    unsigned int remapped[MAX_VECT_LEN];
    unsigned char perm2[MAX_VECT_LEN];
*************** loongarch_expand_vec_perm_const (struct
*** 9434,9496 ****
  expand_perm_const_end:
        if (flag)
  	{
- 	  /* Copy selector vector from memory to vector register for later insn
- 	     gen function.
- 	     If vector's element in floating point value, we cannot fit
- 	     selector argument into insn gen function directly, because of the
- 	     insn template definition.  As a solution, generate a integral mode
- 	     subreg of target, then copy selector vector (that is in integral
- 	     mode) to this subreg.  */
- 	  switch (d->vmode)
- 	    {
- 	    case E_V4DFmode:
- 	      sel = gen_rtx_CONST_VECTOR (E_V4DImode, gen_rtvec_v (d->nelt,
- 								   rperm));
- 	      tmp = simplify_gen_subreg (E_V4DImode, d->target, d->vmode, 0);
- 	      emit_move_insn (tmp, sel);
- 	      break;
- 	    case E_V8SFmode:
- 	      sel = gen_rtx_CONST_VECTOR (E_V8SImode, gen_rtvec_v (d->nelt,
- 								   rperm));
- 	      tmp = simplify_gen_subreg (E_V8SImode, d->target, d->vmode, 0);
- 	      emit_move_insn (tmp, sel);
- 	      break;
- 	    default:
- 	      sel = gen_rtx_CONST_VECTOR (d->vmode, gen_rtvec_v (d->nelt,
- 								 rperm));
- 	      emit_move_insn (d->target, sel);
- 	      break;
- 	    }
- 
  	  target = d->target;
  	  op0 = d->op0;
  	  op1 = d->one_vector_p ? d->op0 : d->op1;
  
! 	  /* We FINALLY can generate xvshuf.* insn.  */
! 	  switch (d->vmode)
! 	    {
! 	    case E_V4DFmode:
! 	      emit_insn (gen_lasx_xvshuf_d_f (target, target, op1, op0));
! 	      break;
! 	    case E_V4DImode:
! 	      emit_insn (gen_lasx_xvshuf_d (target, target, op1, op0));
! 	      break;
! 	    case E_V8SFmode:
! 	      emit_insn (gen_lasx_xvshuf_w_f (target, target, op1, op0));
! 	      break;
! 	    case E_V8SImode:
! 	      emit_insn (gen_lasx_xvshuf_w (target, target, op1, op0));
! 	      break;
! 	    case E_V16HImode:
! 	      emit_insn (gen_lasx_xvshuf_h (target, target, op1, op0));
! 	      break;
! 	    case E_V32QImode:
! 	      emit_insn (gen_lasx_xvshuf_b (target, op1, op0, target));
! 	      break;
! 	    default:
! 	      gcc_unreachable ();
! 	      break;
! 	    }
  
  	  return true;
  	}
--- 9410,9432 ----
  expand_perm_const_end:
        if (flag)
  	{
  	  target = d->target;
  	  op0 = d->op0;
  	  op1 = d->one_vector_p ? d->op0 : d->op1;
  
! 	  machine_mode sel_mode = related_int_vector_mode (d->vmode)
! 	    .require ();
! 	  rtvec sel_v = gen_rtvec_v (d->nelt, rperm);
! 
! 	  /* See the comment in loongarch_expand_lsx_shuffle for why
! 	     we don't simply use a SUBREG to pun target.  */
! 	  rtx sel = force_reg (sel_mode,
! 			       gen_rtx_CONST_VECTOR (sel_mode, sel_v));
! 
! 	  if (d->vmode == E_V32QImode)
! 	    emit_insn (gen_lasx_xvshuf_b (target, op1, op0, sel));
! 	  else
! 	    emit_insn (gen_lasx_xvshuf (d->vmode, target, sel, op1, op0));
  
  	  return true;
  	}
diff -Nrcpad gcc-14-20250725/gcc/config/loongarch/lsx.md gcc-14-20250801/gcc/config/loongarch/lsx.md
*** gcc-14-20250725/gcc/config/loongarch/lsx.md	Fri Jul 25 22:32:12 2025
--- gcc-14-20250801/gcc/config/loongarch/lsx.md	Fri Aug  1 22:32:40 2025
***************
*** 689,697 ****
    DONE;
  })
  
! (define_insn "lsx_vshuf_<lsxfmt_f>"
    [(set (match_operand:LSX_DWH 0 "register_operand" "=f")
! 	(unspec:LSX_DWH [(match_operand:LSX_DWH 1 "register_operand" "0")
  			 (match_operand:LSX_DWH 2 "register_operand" "f")
  			 (match_operand:LSX_DWH 3 "register_operand" "f")]
  			UNSPEC_LSX_VSHUF))]
--- 689,697 ----
    DONE;
  })
  
! (define_insn "@lsx_vshuf_<lsxfmt_f>"
    [(set (match_operand:LSX_DWH 0 "register_operand" "=f")
! 	(unspec:LSX_DWH [(match_operand:<VIMODE> 1 "register_operand" "0")
  			 (match_operand:LSX_DWH 2 "register_operand" "f")
  			 (match_operand:LSX_DWH 3 "register_operand" "f")]
  			UNSPEC_LSX_VSHUF))]
diff -Nrcpad gcc-14-20250725/gcc/cp/ChangeLog gcc-14-20250801/gcc/cp/ChangeLog
*** gcc-14-20250725/gcc/cp/ChangeLog	Fri Jul 25 22:32:12 2025
--- gcc-14-20250801/gcc/cp/ChangeLog	Fri Aug  1 22:32:41 2025
***************
*** 1,3 ****
--- 1,14 ----
+ 2025-07-26  Jason Merrill  <jason@redhat.com>
+ 
+ 	Backported from master:
+ 	2025-07-15  Jason Merrill  <jason@redhat.com>
+ 
+ 	PR c++/120577
+ 	* constexpr.cc (cxx_eval_call_expression): Set
+ 	CONSTRUCTOR_NO_CLEARING on initial value for ctor.
+ 	(cxx_eval_component_reference): Make value-initialization
+ 	of an aggregate member explicit.
+ 
  2025-07-03  Jakub Jelinek  <jakub@redhat.com>
  
  	Backported from master:
diff -Nrcpad gcc-14-20250725/gcc/cp/constexpr.cc gcc-14-20250801/gcc/cp/constexpr.cc
*** gcc-14-20250725/gcc/cp/constexpr.cc	Fri Jul 25 22:32:12 2025
--- gcc-14-20250801/gcc/cp/constexpr.cc	Fri Aug  1 22:32:41 2025
*************** cxx_eval_call_expression (const constexp
*** 3337,3346 ****
  	      && TREE_CODE (new_obj) == COMPONENT_REF
  	      && TREE_CODE (TREE_TYPE (TREE_OPERAND (new_obj, 0))) == UNION_TYPE)
  	    {
  	      tree activate = build2 (INIT_EXPR, TREE_TYPE (new_obj),
! 				      new_obj,
! 				      build_constructor (TREE_TYPE (new_obj),
! 							 NULL));
  	      cxx_eval_constant_expression (ctx, activate,
  					    lval, non_constant_p, overflow_p);
  	      ggc_free (activate);
--- 3337,3346 ----
  	      && TREE_CODE (new_obj) == COMPONENT_REF
  	      && TREE_CODE (TREE_TYPE (TREE_OPERAND (new_obj, 0))) == UNION_TYPE)
  	    {
+ 	      tree ctor = build_constructor (TREE_TYPE (new_obj), NULL);
+ 	      CONSTRUCTOR_NO_CLEARING (ctor) = true;
  	      tree activate = build2 (INIT_EXPR, TREE_TYPE (new_obj),
! 				      new_obj, ctor);
  	      cxx_eval_constant_expression (ctx, activate,
  					    lval, non_constant_p, overflow_p);
  	      ggc_free (activate);
*************** cxx_eval_component_reference (const cons
*** 4731,4736 ****
--- 4731,4746 ----
      }
  
    /* If there's no explicit init for this field, it's value-initialized.  */
+ 
+   if (AGGREGATE_TYPE_P (TREE_TYPE (t)))
+     {
+       /* As in cxx_eval_store_expression, insert an empty CONSTRUCTOR
+ 	 and copy the flags.  */
+       constructor_elt *e = get_or_insert_ctor_field (whole, part);
+       e->value = value = build_constructor (TREE_TYPE (part), NULL);
+       return value;
+     }
+ 
    value = build_value_init (TREE_TYPE (t), tf_warning_or_error);
    return cxx_eval_constant_expression (ctx, value,
  				       lval,
*************** cxx_eval_vec_init_1 (const constexpr_ctx
*** 5497,5502 ****
--- 5507,5515 ----
      return cxx_eval_bare_aggregate (ctx, init, lval,
  				    non_constant_p, overflow_p);
  
+   /* We already checked access when building the VEC_INIT_EXPR.  */
+   deferring_access_check_sentinel acs (dk_deferred);
+ 
    /* For the default constructor, build up a call to the default
       constructor of the element type.  We only need to handle class types
       here, as for a constructor to be constexpr, all members must be
diff -Nrcpad gcc-14-20250725/gcc/testsuite/ChangeLog gcc-14-20250801/gcc/testsuite/ChangeLog
*** gcc-14-20250725/gcc/testsuite/ChangeLog	Fri Jul 25 22:32:13 2025
--- gcc-14-20250801/gcc/testsuite/ChangeLog	Fri Aug  1 22:32:46 2025
***************
*** 1,3 ****
--- 1,82 ----
+ 2025-07-31  Spencer Abson  <spencer.abson@arm.com>
+ 
+ 	Backported from master:
+ 	2025-07-31  Spencer Abson  <spencer.abson@arm.com>
+ 
+ 	PR target/121028
+ 	* gcc.target/aarch64/sme/call_sm_switch_1.c: Tell check-function
+ 	-bodies not to ignore .inst directives, and replace the test for
+ 	"smstart sm" with one for it's encoding.
+ 	* gcc.target/aarch64/sme/call_sm_switch_11.c: Likewise.
+ 	* gcc.target/aarch64/sme/pr121028.c: New test.
+ 
+ 2025-07-31  Jeevitha  <jeevitha@linux.ibm.com>
+ 
+ 	Backported from master:
+ 	2025-07-24  Jeevitha Palanisamy  <jeevitha@linux.ibm.com>
+ 
+ 	PR testsuite/119382
+ 	* gcc.target/powerpc/vsx-builtin-7.c: Add '-fno-ipa-icf' to dg-options.
+ 
+ 2025-07-31  H.J. Lu  <hjl.tools@gmail.com>
+ 
+ 	Backported from master:
+ 	2025-07-30  H.J. Lu  <hjl.tools@gmail.com>
+ 
+ 	PR target/120427
+ 	* gcc.target/i386/pr120427-5.c: New test.
+ 
+ 2025-07-31  liuhongt  <hongtao.liu@intel.com>
+ 
+ 	Backported from master:
+ 	2025-07-30  liuhongt  <hongtao.liu@intel.com>
+ 
+ 	* gcc.target/i386/pr121274.c: New test.
+ 
+ 2025-07-29  H.J. Lu  <hjl.tools@gmail.com>
+ 
+ 	Backported from master:
+ 	2025-06-19  H.J. Lu  <hjl.tools@gmail.com>
+ 
+ 	PR target/120427
+ 	* gcc.target/i386/cold-attribute-4.c: Compile with -Oz.
+ 	* gcc.target/i386/pr120427-1.c: New test.
+ 	* gcc.target/i386/pr120427-2.c: Likewise.
+ 	* gcc.target/i386/pr120427-3.c: Likewise.
+ 	* gcc.target/i386/pr120427-4.c: Likewise.
+ 
+ 2025-07-28  Xi Ruoyao  <xry111@xry111.site>
+ 
+ 	Backported from master:
+ 	2025-07-17  Xi Ruoyao  <xry111@xry111.site>
+ 
+ 	PR target/121064
+ 	* gcc.target/loongarch/pr121064.c: New test.
+ 
+ 2025-07-26  Richard Sandiford  <richard.sandiford@arm.com>
+ 
+ 	Backported from master:
+ 	2025-07-11  Richard Sandiford  <richard.sandiford@arm.com>
+ 
+ 	PR target/121027
+ 	* gcc.target/aarch64/sve/acle/general/perm_1.c: New test.
+ 
+ 2025-07-26  Richard Sandiford  <richard.sandiford@arm.com>
+ 
+ 	Backported from master:
+ 	2024-10-07  Richard Sandiford  <richard.sandiford@arm.com>
+ 
+ 	PR target/121027
+ 	* gcc.target/aarch64/sve/permute_5.c: New test.
+ 
+ 2025-07-26  Jason Merrill  <jason@redhat.com>
+ 
+ 	Backported from master:
+ 	2025-07-15  Jason Merrill  <jason@redhat.com>
+ 
+ 	PR c++/120577
+ 	* g++.dg/cpp2a/constexpr-union9.C: New test.
+ 
  2025-07-22  Haochen Gui  <guihaoc@gcc.gnu.org>
  
  	Backported from master:
diff -Nrcpad gcc-14-20250725/gcc/testsuite/g++.dg/cpp0x/constexpr-array30.C gcc-14-20250801/gcc/testsuite/g++.dg/cpp0x/constexpr-array30.C
*** gcc-14-20250725/gcc/testsuite/g++.dg/cpp0x/constexpr-array30.C	Thu Jan  1 00:00:00 1970
--- gcc-14-20250801/gcc/testsuite/g++.dg/cpp0x/constexpr-array30.C	Fri Aug  1 22:32:49 2025
***************
*** 0 ****
--- 1,22 ----
+ // PR c++/120800
+ // { dg-do compile { target c++11 } }
+ 
+ template<typename T>
+ struct Container
+ {
+  T m_data[1] {};
+ };
+ 
+ class Element
+ {
+ private:
+  Element() = default;
+ 
+ private:
+  bool m_bool1 { false };
+  bool m_bool2;
+ 
+  friend struct Container<Element>;
+ };
+ 
+ Container<Element> element;
diff -Nrcpad gcc-14-20250725/gcc/testsuite/g++.dg/cpp2a/constexpr-union9.C gcc-14-20250801/gcc/testsuite/g++.dg/cpp2a/constexpr-union9.C
*** gcc-14-20250725/gcc/testsuite/g++.dg/cpp2a/constexpr-union9.C	Thu Jan  1 00:00:00 1970
--- gcc-14-20250801/gcc/testsuite/g++.dg/cpp2a/constexpr-union9.C	Fri Aug  1 22:32:50 2025
***************
*** 0 ****
--- 1,33 ----
+ // PR c++/120577
+ // { dg-do compile { target c++20 } }
+ 
+ template <class _Tp> struct optional {
+   union {
+     _Tp __val_;
+   };
+   template <class... _Args>
+   constexpr optional(_Args... __args)
+       : __val_(__args...) {}
+ };
+ template <class _Tp, class... _Args>
+ constexpr optional<_Tp> make_optional(_Args... __args) {
+   return optional<_Tp>(__args...);
+ }
+ 
+ struct __non_trivial_if {
+   constexpr __non_trivial_if() {}
+ };
+ struct allocator : __non_trivial_if {};
+ struct __padding {};
+ struct __short {
+   [[__no_unique_address__]] __padding __padding_;
+   int __data_;
+ };
+ struct basic_string {
+   union {
+     __short __s;
+   };
+   [[__no_unique_address__]] allocator __alloc_;
+   constexpr basic_string(int, int) {}
+ };
+ auto opt = make_optional<basic_string>(4, 'X');
diff -Nrcpad gcc-14-20250725/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_1.c gcc-14-20250801/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_1.c
*** gcc-14-20250725/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_1.c	Fri Jul 25 22:32:33 2025
--- gcc-14-20250801/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_1.c	Fri Aug  1 22:33:02 2025
***************
*** 1,5 ****
  // { dg-options "-O -fomit-frame-pointer -fno-optimize-sibling-calls -funwind-tables" }
! // { dg-final { check-function-bodies "**" "" } }
  
  void ns_callee ();
   void s_callee () [[arm::streaming]];
--- 1,5 ----
  // { dg-options "-O -fomit-frame-pointer -fno-optimize-sibling-calls -funwind-tables" }
! // { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {\t\.inst} } }
  
  void ns_callee ();
   void s_callee () [[arm::streaming]];
*************** sc_caller_x1 (int *ptr, int a) [[arm::st
*** 218,224 ****
  **	bl	ns_callee_stack
  **	ldr	x16, \[x29, #?16\]
  **	tbz	x16, 0, .*
! **	smstart	sm
  **	...
  */
  void
--- 218,224 ----
  **	bl	ns_callee_stack
  **	ldr	x16, \[x29, #?16\]
  **	tbz	x16, 0, .*
! **	.inst 0xd503437f // smstart sm
  **	...
  */
  void
diff -Nrcpad gcc-14-20250725/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_11.c gcc-14-20250801/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_11.c
*** gcc-14-20250725/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_11.c	Fri Jul 25 22:32:33 2025
--- gcc-14-20250801/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_11.c	Fri Aug  1 22:33:02 2025
***************
*** 1,5 ****
  // { dg-options "-O -fomit-frame-pointer -fno-optimize-sibling-calls -funwind-tables -mtrack-speculation" }
! // { dg-final { check-function-bodies "**" "" } }
  
  void ns_callee ();
   void s_callee () [[arm::streaming]];
--- 1,6 ----
  // { dg-options "-O -fomit-frame-pointer -fno-optimize-sibling-calls -funwind-tables -mtrack-speculation" }
! // { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {\t\.inst} } }
! 
  
  void ns_callee ();
   void s_callee () [[arm::streaming]];
*************** sc_caller_x1 (int *ptr, int a) [[arm::st
*** 196,202 ****
  **	tst	x16, #?1
  **	beq	[^\n]*
  **	csel	x15, x15, xzr, ne
! **	smstart	sm
  **	...
  */
  void
--- 197,203 ----
  **	tst	x16, #?1
  **	beq	[^\n]*
  **	csel	x15, x15, xzr, ne
! **	.inst 0xd503437f // smstart sm
  **	...
  */
  void
diff -Nrcpad gcc-14-20250725/gcc/testsuite/gcc.target/aarch64/sme/pr121028.c gcc-14-20250801/gcc/testsuite/gcc.target/aarch64/sme/pr121028.c
*** gcc-14-20250725/gcc/testsuite/gcc.target/aarch64/sme/pr121028.c	Thu Jan  1 00:00:00 1970
--- gcc-14-20250801/gcc/testsuite/gcc.target/aarch64/sme/pr121028.c	Fri Aug  1 22:33:02 2025
***************
*** 0 ****
--- 1,46 ----
+ // PR121028
+ // { dg-do assemble { target aarch64_asm_sme_ok } }
+ // { dg-options "-O --save-temps" }
+ // { dg-final { check-function-bodies "**" "" "" { target "*-*-*" } {\t\.inst} } }
+ 
+ void ns_callee ();
+ 
+ /*
+ ** sc_caller_sme:
+ **	...
+ **	mrs	x16, svcr
+ **	str	x16, \[x29, #?16\]
+ **	ldr	x16, \[x29, #?16\]
+ **	tbz	x16, 0, .*
+ **	smstop	sm
+ **	bl	ns_callee
+ **	ldr	x16, \[x29, #?16\]
+ **	tbz	x16, 0, .*
+ **	smstart	sm
+ **	...
+ */
+ void sc_caller_sme() __arm_streaming_compatible
+ {
+     ns_callee ();
+ }
+ 
+ #pragma GCC target "+nosme"
+ 
+ /*
+ ** sc_caller_nosme:
+ **	...
+ **	bl	__arm_sme_state
+ **	str	x0, \[x29, #?16\]
+ **	ldr	x16, \[x29, #?16\]
+ **	tbz	x16, 0, .*
+ **	.inst 0xd503427f // smstop sm
+ **	bl	ns_callee
+ **	ldr	x16, \[x29, #?16\]
+ **	tbz	x16, 0, .*
+ **	.inst 0xd503437f // smstart sm
+ **	...
+ */
+ void sc_caller_nosme() __arm_streaming_compatible
+ {
+     ns_callee ();
+ }
diff -Nrcpad gcc-14-20250725/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_1.c gcc-14-20250801/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_1.c
*** gcc-14-20250725/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_1.c	Thu Jan  1 00:00:00 1970
--- gcc-14-20250801/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_1.c	Fri Aug  1 22:33:02 2025
***************
*** 0 ****
--- 1,14 ----
+ /* { dg-options "-O2 -msve-vector-bits=256" } */
+ 
+ #include <arm_sve.h>
+ typedef svbfloat16_t vls_bfloat16_t __attribute__((arm_sve_vector_bits(32 * 8)));
+ svbfloat16_t foo(vls_bfloat16_t a, vls_bfloat16_t b)
+ {
+   svbfloat16_t zero = svreinterpret_bf16_f32 (svdup_n_f32 (0.0f));
+   return svzip2_bf16(zero, svuzp1_bf16(a,b));
+ }
+ 
+ 
+ /* { dg-final { scan-assembler-times {\tuzp1\t} 1 } } */
+ /* { dg-final { scan-assembler-times {\tzip2\t} 1 } } */
+ /* { dg-final { scan-assembler-not {\ttbl\t} } } */
diff -Nrcpad gcc-14-20250725/gcc/testsuite/gcc.target/aarch64/sve/permute_5.c gcc-14-20250801/gcc/testsuite/gcc.target/aarch64/sve/permute_5.c
*** gcc-14-20250725/gcc/testsuite/gcc.target/aarch64/sve/permute_5.c	Thu Jan  1 00:00:00 1970
--- gcc-14-20250801/gcc/testsuite/gcc.target/aarch64/sve/permute_5.c	Fri Aug  1 22:33:02 2025
***************
*** 0 ****
--- 1,10 ----
+ /* { dg-options "-O -msve-vector-bits=256" } */
+ 
+ typedef __SVBfloat16_t vbfloat16 __attribute__((arm_sve_vector_bits(256)));
+ 
+ vbfloat16
+ foo (vbfloat16 x, vbfloat16 y)
+ {
+   return __builtin_shufflevector (x, y, 0, 2, 1, 3, 16, 19, 17, 18,
+ 				  8, 9, 10, 11, 23, 22, 21, 20);
+ }
diff -Nrcpad gcc-14-20250725/gcc/testsuite/gcc.target/i386/cold-attribute-4.c gcc-14-20250801/gcc/testsuite/gcc.target/i386/cold-attribute-4.c
*** gcc-14-20250725/gcc/testsuite/gcc.target/i386/cold-attribute-4.c	Fri Jul 25 22:32:37 2025
--- gcc-14-20250801/gcc/testsuite/gcc.target/i386/cold-attribute-4.c	Fri Aug  1 22:33:14 2025
***************
*** 1,5 ****
  /* { dg-do compile } */
! /* { dg-options "-O2" } */
  #include <string.h>
  
  int
--- 1,5 ----
  /* { dg-do compile } */
! /* { dg-options "-Oz" } */
  #include <string.h>
  
  int
diff -Nrcpad gcc-14-20250725/gcc/testsuite/gcc.target/i386/pr120427-1.c gcc-14-20250801/gcc/testsuite/gcc.target/i386/pr120427-1.c
*** gcc-14-20250725/gcc/testsuite/gcc.target/i386/pr120427-1.c	Thu Jan  1 00:00:00 1970
--- gcc-14-20250801/gcc/testsuite/gcc.target/i386/pr120427-1.c	Fri Aug  1 22:33:16 2025
***************
*** 0 ****
--- 1,28 ----
+ /* { dg-do compile } */
+ /* { dg-options "-O2 -mtune=sapphirerapids" } */
+ /* { dg-final { scan-assembler-not "and\[lq\]?\[\\t \]+\\\$0, \[0-9\]*\\(" } } */
+ 
+ struct __pthread_mutex_s
+ {
+   int __lock;
+   unsigned int __count;
+   int __owner;
+   unsigned int __nusers;
+   int __kind;
+   short __spins;
+   short __elision;
+   void *p[2];
+ };
+ typedef union
+ {
+   struct __pthread_mutex_s __data;
+   char __size[40];
+   long int __align;
+ } pthread_mutex_t;
+ typedef struct { pthread_mutex_t mutex; } __rtld_lock_recursive_t;
+ void
+ foo (__rtld_lock_recursive_t *lock, int i)
+ {
+   lock[i] = (__rtld_lock_recursive_t) {{ { 0, 0, 0, 0, 1,
+       0, 0, { ((void *)0) , ((void *)0) } } }};
+ }
diff -Nrcpad gcc-14-20250725/gcc/testsuite/gcc.target/i386/pr120427-2.c gcc-14-20250801/gcc/testsuite/gcc.target/i386/pr120427-2.c
*** gcc-14-20250725/gcc/testsuite/gcc.target/i386/pr120427-2.c	Thu Jan  1 00:00:00 1970
--- gcc-14-20250801/gcc/testsuite/gcc.target/i386/pr120427-2.c	Fri Aug  1 22:33:16 2025
***************
*** 0 ****
--- 1,28 ----
+ /* { dg-do compile } */
+ /* { dg-options "-O2 -mtune=sapphirerapids" } */
+ /* { dg-final { scan-assembler-not "or\[lq\]?\[\\t \]+\\\$-1, \[0-9\]*\\(" } } */
+ 
+ struct __pthread_mutex_s
+ {
+   int __lock;
+   unsigned int __count;
+   int __owner;
+   unsigned int __nusers;
+   int __kind;
+   short __spins;
+   short __elision;
+   void *p[2];
+ };
+ typedef union
+ {
+   struct __pthread_mutex_s __data;
+   char __size[40];
+   long int __align;
+ } pthread_mutex_t;
+ typedef struct { pthread_mutex_t mutex; } __rtld_lock_recursive_t;
+ void
+ foo (__rtld_lock_recursive_t *lock, int i)
+ {
+   lock[i] = (__rtld_lock_recursive_t) {{ { -1, -1, -1, -1, 1,
+       -1, -1, { ((void *)-1) , ((void *)-1) } } }};
+ }
diff -Nrcpad gcc-14-20250725/gcc/testsuite/gcc.target/i386/pr120427-3.c gcc-14-20250801/gcc/testsuite/gcc.target/i386/pr120427-3.c
*** gcc-14-20250725/gcc/testsuite/gcc.target/i386/pr120427-3.c	Thu Jan  1 00:00:00 1970
--- gcc-14-20250801/gcc/testsuite/gcc.target/i386/pr120427-3.c	Fri Aug  1 22:33:16 2025
***************
*** 0 ****
--- 1,45 ----
+ /* { dg-do compile } */
+ /* { dg-options "-O2" } */
+ 
+ typedef int SItype __attribute__ ((mode (SI)));
+ typedef unsigned int USItype __attribute__ ((mode (SI)));
+ typedef unsigned int UDItype __attribute__ ((mode (DI)));
+ typedef UDItype __attribute__ ((__may_alias__)) bar_t;
+ 
+ static inline __attribute__((__always_inline__)) SItype
+ bar (const bar_t **p, SItype prec)
+ {
+   bar_t mslimb = 0;
+   SItype i = 20;
+   SItype n = ((USItype) prec) % 4;
+   if (n)
+     {
+       prec -= n;
+       if (prec == 0)
+ 	return 1;
+       mslimb = (*p)[i];
+     }
+   while (mslimb == 0)
+     {
+       prec -= 4;
+       if (prec == 0)
+ 	return 1;
+       --i;
+       mslimb = (*p)[i];
+     }
+   return prec;
+ }
+ UDItype
+ foo (const bar_t *i, SItype iprec)
+ {
+   iprec = bar (&i, iprec);
+   USItype aiprec = iprec < 0 ? -iprec : iprec;
+   bar_t msb = *i;
+   UDItype mantissa = 0;
+   if (aiprec % 4)
+     msb &= ((bar_t) 1 << aiprec) - 1;
+   if (aiprec >= 54)
+     mantissa = (UDItype) msb << 32;
+ 
+   return (mantissa ^ (UDItype) 0x20000000000000);
+ }
diff -Nrcpad gcc-14-20250725/gcc/testsuite/gcc.target/i386/pr120427-4.c gcc-14-20250801/gcc/testsuite/gcc.target/i386/pr120427-4.c
*** gcc-14-20250725/gcc/testsuite/gcc.target/i386/pr120427-4.c	Thu Jan  1 00:00:00 1970
--- gcc-14-20250801/gcc/testsuite/gcc.target/i386/pr120427-4.c	Fri Aug  1 22:33:16 2025
***************
*** 0 ****
--- 1,6 ----
+ /* { dg-do compile } */
+ /* { dg-options "-O2" } */
+ 
+ #include "cold-attribute-4.c"
+ 
+ /* { dg-final { scan-assembler "movl" } } */
diff -Nrcpad gcc-14-20250725/gcc/testsuite/gcc.target/i386/pr120427-5.c gcc-14-20250801/gcc/testsuite/gcc.target/i386/pr120427-5.c
*** gcc-14-20250725/gcc/testsuite/gcc.target/i386/pr120427-5.c	Thu Jan  1 00:00:00 1970
--- gcc-14-20250801/gcc/testsuite/gcc.target/i386/pr120427-5.c	Fri Aug  1 22:33:16 2025
***************
*** 0 ****
--- 1,10 ----
+ /* { dg-do compile { target { ! ia32 } } } */
+ /* { dg-options "-Oz" } */
+ 
+ long long
+ func1 (void)
+ {
+   return -1;
+ }
+ /* { dg-final { scan-assembler-times "pushq\[ \\t\]+\\\$-1" 1 } } */
+ /* { dg-final { scan-assembler-times "popq\[ \\t\]+%rax" 1 } } */
diff -Nrcpad gcc-14-20250725/gcc/testsuite/gcc.target/i386/pr121274.c gcc-14-20250801/gcc/testsuite/gcc.target/i386/pr121274.c
*** gcc-14-20250725/gcc/testsuite/gcc.target/i386/pr121274.c	Thu Jan  1 00:00:00 1970
--- gcc-14-20250801/gcc/testsuite/gcc.target/i386/pr121274.c	Fri Aug  1 22:33:16 2025
***************
*** 0 ****
--- 1,24 ----
+ /* { dg-do compile { target { ! ia32 } } } */
+ /* { dg-options "-march=x86-64-v4 -O2" } */
+ /* { dg-final { scan-assembler-not "vpextrq" } } */
+ /* { dg-final { scan-assembler-not "vpinsrq" } } */
+ 
+ typedef int v16si __attribute__((vector_size(64)));
+ typedef int v4si __attribute__((vector_size(16)));
+ 
+ v4si f(v16si x)
+ {
+   return __builtin_shufflevector(x, x, 0, 1, 2, 3);
+ }
+ 
+ v4si g(v16si x)
+ {
+ return __builtin_shufflevector(x, x, 4, 5, 6, 7);
+ }
+ 
+ v4si f1(__int128 *x)
+ {
+   __int128 t = *x;
+   asm("":"+x"(t));
+   return (v4si)t;
+ }
diff -Nrcpad gcc-14-20250725/gcc/testsuite/gcc.target/loongarch/pr121064.c gcc-14-20250801/gcc/testsuite/gcc.target/loongarch/pr121064.c
*** gcc-14-20250725/gcc/testsuite/gcc.target/loongarch/pr121064.c	Thu Jan  1 00:00:00 1970
--- gcc-14-20250801/gcc/testsuite/gcc.target/loongarch/pr121064.c	Fri Aug  1 22:33:17 2025
***************
*** 0 ****
--- 1,38 ----
+ /* { dg-require-effective-target loongarch_sx_hw } */
+ /* { dg-do run } */
+ /* { dg-options "-march=loongarch64 -mfpu=64 -mlsx -O3" } */
+ 
+ typedef __INT32_TYPE__ int32_t;
+ typedef unsigned __INT32_TYPE__ uint32_t;
+ 
+ __attribute__ ((noipa)) static int32_t
+ long_filter_ehigh_3830_1 (int32_t *buffer, int length)
+ {
+   int i, j;
+   int32_t dotprod = 0;
+   int32_t delay[4] = { 0 };
+   uint32_t coeffs[4] = { 0 };
+ 
+   for (i = 0; i < length; i++)
+     {
+       dotprod = 0;
+       for (j = 3; j >= 0; j--)
+         {
+           dotprod += delay[j] * coeffs[j];
+           coeffs[j] += ((delay[j] >> 31) | 1);
+         }
+       for (j = 3; j > 0; j--)
+         delay[j] = delay[j - 1];
+       delay[0] = buffer[i];
+     }
+ 
+   return dotprod;
+ }
+ 
+ int
+ main ()
+ {
+   int32_t buffer[] = { -1, 1 };
+   if (long_filter_ehigh_3830_1 (buffer, 2) != -1)
+     __builtin_trap ();
+ }
diff -Nrcpad gcc-14-20250725/gcc/testsuite/gcc.target/powerpc/vsx-builtin-7.c gcc-14-20250801/gcc/testsuite/gcc.target/powerpc/vsx-builtin-7.c
*** gcc-14-20250725/gcc/testsuite/gcc.target/powerpc/vsx-builtin-7.c	Fri Jul 25 22:32:42 2025
--- gcc-14-20250801/gcc/testsuite/gcc.target/powerpc/vsx-builtin-7.c	Fri Aug  1 22:33:19 2025
***************
*** 1,7 ****
  /* { dg-do compile { target { powerpc*-*-* } } } */
  /* { dg-skip-if "" { powerpc*-*-darwin* } } */
  /* { dg-require-effective-target powerpc_vsx_ok } */
! /* { dg-options "-O2 -mdejagnu-cpu=power7 -fno-inline-functions" } */
  
  /* Test simple extract/insert/slat operations.  Make sure all types are
     supported with various options.  */
--- 1,15 ----
  /* { dg-do compile { target { powerpc*-*-* } } } */
  /* { dg-skip-if "" { powerpc*-*-darwin* } } */
  /* { dg-require-effective-target powerpc_vsx_ok } */
! /* { dg-options "-O2 -mdejagnu-cpu=power7 -fno-inline-functions -fno-ipa-icf" } */
! 
! /* PR testsuite/119382
!    Note: Added -fno-ipa-icf to disable Interprocedural Identical Code
!    Folding (ICF). Without this, insert_di_0_v2 is merged with insert_di_0
!    due to improved alias analysis introduced in commit r15-7961-gdc47161c1f32c3.
!    This results in the compiler replacing insert_di_0_v2 with a tail call to
!    insert_di_0, altering expected test behavior. Disabling ICF ensures correct
!    execution of the test.  */
  
  /* Test simple extract/insert/slat operations.  Make sure all types are
     supported with various options.  */
diff -Nrcpad gcc-14-20250725/gcc/tree-vect-stmts.cc gcc-14-20250801/gcc/tree-vect-stmts.cc
*** gcc-14-20250725/gcc/tree-vect-stmts.cc	Fri Jul 25 22:32:54 2025
--- gcc-14-20250801/gcc/tree-vect-stmts.cc	Fri Aug  1 22:34:14 2025
*************** supportable_widening_operation (vec_info
*** 14263,14268 ****
--- 14263,14270 ----
  
        internal_fn lo, hi, even, odd;
        lookup_hilo_internal_fn (ifn, &lo, &hi);
+       if (BYTES_BIG_ENDIAN)
+ 	std::swap (lo, hi);
        *code1 = as_combined_fn (lo);
        *code2 = as_combined_fn (hi);
        optab1 = direct_internal_fn_optab (lo, {vectype, vectype});
diff -Nrcpad gcc-14-20250725/libsanitizer/ChangeLog gcc-14-20250801/libsanitizer/ChangeLog
*** gcc-14-20250725/libsanitizer/ChangeLog	Fri Jul 25 22:33:00 2025
--- gcc-14-20250801/libsanitizer/ChangeLog	Fri Aug  1 22:34:17 2025
***************
*** 1,3 ****
--- 1,14 ----
+ 2025-07-31  Florian Weimer  <fweimer@redhat.com>
+ 
+ 	Backported from master:
+ 	2025-05-02  Florian Weimer  <fweimer@redhat.com>
+ 		    Tom Stellard  <tstellar@redhat.com>
+ 
+ 	* sanitizer_common/sanitizer_common_interceptors_ioctl.inc: Cherry
+ 	picked from LLVM commit 59978b21ad9c65276ee8e14f26759691b8a65763.
+ 	* sanitizer_common/sanitizer_platform_limits_posix.cpp: Likewise.
+ 	* sanitizer_common/sanitizer_platform_limits_posix.h: Likewise.
+ 
  2025-05-23  Release Manager
  
  	* GCC 14.3.0 released.
diff -Nrcpad gcc-14-20250725/libsanitizer/sanitizer_common/sanitizer_common_interceptors_ioctl.inc gcc-14-20250801/libsanitizer/sanitizer_common/sanitizer_common_interceptors_ioctl.inc
*** gcc-14-20250725/libsanitizer/sanitizer_common/sanitizer_common_interceptors_ioctl.inc	Fri Jul 25 22:33:00 2025
--- gcc-14-20250801/libsanitizer/sanitizer_common/sanitizer_common_interceptors_ioctl.inc	Fri Aug  1 22:34:17 2025
*************** static void ioctl_table_fill() {
*** 338,354 ****
    _(SOUND_PCM_WRITE_CHANNELS, WRITE, sizeof(int));
    _(SOUND_PCM_WRITE_FILTER, WRITE, sizeof(int));
    _(TCFLSH, NONE, 0);
- #if SANITIZER_GLIBC
-   _(TCGETA, WRITE, struct_termio_sz);
- #endif
    _(TCGETS, WRITE, struct_termios_sz);
    _(TCSBRK, NONE, 0);
    _(TCSBRKP, NONE, 0);
- #if SANITIZER_GLIBC
-   _(TCSETA, READ, struct_termio_sz);
-   _(TCSETAF, READ, struct_termio_sz);
-   _(TCSETAW, READ, struct_termio_sz);
- #endif
    _(TCSETS, READ, struct_termios_sz);
    _(TCSETSF, READ, struct_termios_sz);
    _(TCSETSW, READ, struct_termios_sz);
--- 338,346 ----
diff -Nrcpad gcc-14-20250725/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.cpp gcc-14-20250801/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.cpp
*** gcc-14-20250725/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.cpp	Fri Jul 25 22:33:00 2025
--- gcc-14-20250801/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.cpp	Fri Aug  1 22:34:17 2025
*************** unsigned struct_ElfW_Phdr_sz = sizeof(El
*** 479,487 ****
    unsigned struct_input_id_sz = sizeof(struct input_id);
    unsigned struct_mtpos_sz = sizeof(struct mtpos);
    unsigned struct_rtentry_sz = sizeof(struct rtentry);
- #if SANITIZER_GLIBC || SANITIZER_ANDROID
-   unsigned struct_termio_sz = sizeof(struct termio);
- #endif
    unsigned struct_vt_consize_sz = sizeof(struct vt_consize);
    unsigned struct_vt_sizes_sz = sizeof(struct vt_sizes);
    unsigned struct_vt_stat_sz = sizeof(struct vt_stat);
--- 479,484 ----
*************** unsigned struct_ElfW_Phdr_sz = sizeof(El
*** 758,770 ****
    unsigned IOCTL_SOUND_PCM_WRITE_FILTER = SOUND_PCM_WRITE_FILTER;
  #endif // SOUND_VERSION
    unsigned IOCTL_TCFLSH = TCFLSH;
-   unsigned IOCTL_TCGETA = TCGETA;
    unsigned IOCTL_TCGETS = TCGETS;
    unsigned IOCTL_TCSBRK = TCSBRK;
    unsigned IOCTL_TCSBRKP = TCSBRKP;
-   unsigned IOCTL_TCSETA = TCSETA;
-   unsigned IOCTL_TCSETAF = TCSETAF;
-   unsigned IOCTL_TCSETAW = TCSETAW;
    unsigned IOCTL_TCSETS = TCSETS;
    unsigned IOCTL_TCSETSF = TCSETSF;
    unsigned IOCTL_TCSETSW = TCSETSW;
--- 755,763 ----
diff -Nrcpad gcc-14-20250725/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h gcc-14-20250801/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h
*** gcc-14-20250725/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h	Fri Jul 25 22:33:00 2025
--- gcc-14-20250801/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h	Fri Aug  1 22:34:17 2025
*************** extern unsigned struct_hd_geometry_sz;
*** 1012,1018 ****
  extern unsigned struct_input_absinfo_sz;
  extern unsigned struct_input_id_sz;
  extern unsigned struct_mtpos_sz;
- extern unsigned struct_termio_sz;
  extern unsigned struct_vt_consize_sz;
  extern unsigned struct_vt_sizes_sz;
  extern unsigned struct_vt_stat_sz;
--- 1012,1017 ----
*************** extern unsigned IOCTL_SNDCTL_COPR_SENDMS
*** 1257,1269 ****
  extern unsigned IOCTL_SNDCTL_COPR_WCODE;
  extern unsigned IOCTL_SNDCTL_COPR_WDATA;
  extern unsigned IOCTL_TCFLSH;
- extern unsigned IOCTL_TCGETA;
  extern unsigned IOCTL_TCGETS;
  extern unsigned IOCTL_TCSBRK;
  extern unsigned IOCTL_TCSBRKP;
- extern unsigned IOCTL_TCSETA;
- extern unsigned IOCTL_TCSETAF;
- extern unsigned IOCTL_TCSETAW;
  extern unsigned IOCTL_TCSETS;
  extern unsigned IOCTL_TCSETSF;
  extern unsigned IOCTL_TCSETSW;
--- 1256,1264 ----
