diff -Nrcpad gcc-14-20250808/LAST_UPDATED gcc-14-20250815/LAST_UPDATED
*** gcc-14-20250808/LAST_UPDATED	Fri Aug  8 22:34:21 2025
--- gcc-14-20250815/LAST_UPDATED	Fri Aug 15 22:33:04 2025
***************
*** 1 ****
! Obtained from git: releases/gcc-14 revision b471cfe61cc586877b40ed3c2dd39583d9ef2e5a
--- 1 ----
! Obtained from git: releases/gcc-14 revision b41115c1907f9277e91367700b9da429d1aaa49f
diff -Nrcpad gcc-14-20250808/MD5SUMS gcc-14-20250815/MD5SUMS
*** gcc-14-20250808/MD5SUMS	Fri Aug  8 22:34:24 2025
--- gcc-14-20250815/MD5SUMS	Fri Aug 15 22:33:07 2025
***************
*** 1,5 ****
  # This file contains the MD5 checksums of the files in the
! # gcc-14-20250808.tar.xz tarball.
  #
  # Besides verifying that all files in the tarball were correctly expanded,
  # it also can be used to determine if any files have changed since the
--- 1,5 ----
  # This file contains the MD5 checksums of the files in the
! # gcc-14-20250815.tar.xz tarball.
  #
  # Besides verifying that all files in the tarball were correctly expanded,
  # it also can be used to determine if any files have changed since the
*************** fc9280b02bc68e4fb1ef8d51ccc25061  Change
*** 23,29 ****
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--- 23,29 ----
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*** 505,511 ****
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--- 505,511 ----
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*** 541,547 ****
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--- 541,547 ----
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*************** fb5f673cea6166ff90878e05bfa7dfe0  gcc/bu
*** 3149,3155 ****
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--- 3149,3155 ----
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*************** d9397260c45e57a1d9da554ae2e2a646  gcc/co
*** 3349,3358 ****
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--- 3349,3358 ----
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*************** d3d0a9db4cb45433208c51520e54f3bb  gcc/co
*** 3364,3378 ****
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--- 3364,3378 ----
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*************** d0eb4ba200acb78424e4f81fef87ed74  gcc/co
*** 3395,3401 ****
  1e10a63f5542acfb7d0e13c5500255fb  gcc/config/aarch64/geniterators.sh
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--- 3395,3401 ----
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*************** fccc6d65638a2ce66ebc6b06766912c2  gcc/co
*** 4063,4069 ****
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--- 4063,4069 ----
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*************** fda2bfdc2de3eafec6a40c91767e52d7  gcc/co
*** 4295,4301 ****
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--- 4295,4301 ----
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*************** ea6cc43b3fa3313db4228947eed2152e  gcc/co
*** 4307,4313 ****
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--- 4307,4313 ----
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*************** d36a2aabdf8da39363d9be0efef739b0  gcc/co
*** 5361,5367 ****
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--- 5361,5367 ----
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*************** c8f7d73c0019711303d537b68567d9c3  gcc/do
*** 5811,5817 ****
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--- 5811,5817 ----
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*************** e8a9eb01b9451a357155e7152df1c669  gcc/ta
*** 8060,8066 ****
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--- 8060,8066 ----
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*************** af40dade74feb71f52277a623af87930  gcc/te
*** 34867,34872 ****
--- 34867,34874 ----
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*************** ab6c5e333d0a740ae5ecff69966813a2  gcc/te
*** 35005,35010 ****
--- 35007,35013 ----
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*************** c317cb696a26bea6d51beb4b38e72094  gcc/te
*** 55610,55616 ****
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--- 55613,55619 ----
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*************** da2e0ca1db6e6911aecfa27990b0f4e7  gcc/te
*** 55636,55643 ****
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--- 55639,55646 ----
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*************** df9a1b5d24aec3bc8a0ef502ec0a64b9  gcc/te
*** 59208,59213 ****
--- 59211,59217 ----
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*************** ae44d68f203e7d5a17d19738cfbc53a0  gcc/te
*** 62050,62055 ****
--- 62054,62065 ----
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*************** bf328a0ed3cadaf01cdcd516cb16a2eb  gcc/te
*** 62077,62082 ****
--- 62087,62093 ----
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*************** f5a1252b1fe24ea2b97ff3762c399ed9  gcc/te
*** 75219,75224 ****
--- 75230,75241 ----
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*************** b4671c279162dd2c1fd844929bdbbc6b  gcc/te
*** 78432,78437 ****
--- 78449,78455 ----
  dbfbd76701c5c3e6c8ed37ced1ba9cc7  gcc/testsuite/gcc.target/loongarch/pr119084.c
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*************** c4d8ec89484f8330ae0008d131fedf28  gcc/te
*** 108126,108132 ****
  d5c788891580183c0162d61bee2606c9  gcc/testsuite/lib/mike-g++.exp
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! f89b045f2842e5ff03497a49f6252c55  gcc/testsuite/lib/multiline.exp
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--- 108144,108150 ----
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*************** a418f2a12bc2c1ec76cd9ee5444af0f5  gcc/te
*** 108154,108160 ****
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! 0c56c9a66c5c003d0e7bdeb6233332fa  gcc/testsuite/lib/target-supports.exp
  d84983886d0708605af864226f6beac0  gcc/testsuite/lib/target-utils.exp
  64f7537fc29d3ab37e44b5aaf37c5fb4  gcc/testsuite/lib/timeout-dg.exp
  75cfa45901d445df376345935b79fa37  gcc/testsuite/lib/timeout.exp
--- 108172,108178 ----
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  d84983886d0708605af864226f6beac0  gcc/testsuite/lib/target-utils.exp
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  75cfa45901d445df376345935b79fa37  gcc/testsuite/lib/timeout.exp
*************** b8c85c8c8e7d96bdee3b36f360d85909  libgcc
*** 111287,111293 ****
  a077f95c64de11e67e5d9d909ec45b8c  libgcc/config/aarch64/heap-trampoline.c
  2f4f1a66016e8441301c8e14f69983cf  libgcc/config/aarch64/libgcc-sme.ver
  3b6e3550bfe5c4e5ec25b99108f46513  libgcc/config/aarch64/libgcc-softfp.ver
! 56a1f2d9dfab63cbe5956843fabf7d30  libgcc/config/aarch64/linux-unwind.h
  04307fc9daa7af7f2d0ca9ba5bc55e33  libgcc/config/aarch64/lse-init.c
  2c6803770e388ebace8cd426f33ffec6  libgcc/config/aarch64/lse.S
  e271966ce38209c96e6f569a9f952283  libgcc/config/aarch64/sfp-exceptions.c
--- 111305,111311 ----
  a077f95c64de11e67e5d9d909ec45b8c  libgcc/config/aarch64/heap-trampoline.c
  2f4f1a66016e8441301c8e14f69983cf  libgcc/config/aarch64/libgcc-sme.ver
  3b6e3550bfe5c4e5ec25b99108f46513  libgcc/config/aarch64/libgcc-softfp.ver
! 5bacf834d1391e577c694cf4a7e46c11  libgcc/config/aarch64/linux-unwind.h
  04307fc9daa7af7f2d0ca9ba5bc55e33  libgcc/config/aarch64/lse-init.c
  2c6803770e388ebace8cd426f33ffec6  libgcc/config/aarch64/lse.S
  e271966ce38209c96e6f569a9f952283  libgcc/config/aarch64/sfp-exceptions.c
diff -Nrcpad gcc-14-20250808/gcc/ChangeLog gcc-14-20250815/gcc/ChangeLog
*** gcc-14-20250808/gcc/ChangeLog	Fri Aug  8 22:32:31 2025
--- gcc-14-20250815/gcc/ChangeLog	Fri Aug 15 22:32:06 2025
***************
*** 1,3 ****
--- 1,107 ----
+ 2025-08-14  Richard Sandiford  <richard.sandiford@arm.com>
+ 
+ 	Backported from master:
+ 	2025-08-14  Richard Sandiford  <richard.sandiford@arm.com>
+ 
+ 	PR target/121414
+ 	* config/aarch64/aarch64.cc (aarch64_is_variant_pcs): New function,
+ 	split out from...
+ 	(aarch64_asm_output_variant_pcs): ...here.  Handle various types
+ 	of SME function type.
+ 
+ 2025-08-14  Richard Sandiford  <richard.sandiford@arm.com>
+ 
+ 	Backported from master:
+ 	2025-08-14  Richard Sandiford  <richard.sandiford@arm.com>
+ 
+ 	PR target/121294
+ 	* config/aarch64/aarch64.md (UNSPEC_REV_PRED): New unspec.
+ 	* config/aarch64/aarch64-sve.md (@aarch64_sve_rev<mode>_acle)
+ 	(*aarch64_sve_rev<mode>_acle): New patterns.
+ 	* config/aarch64/aarch64-sve-builtins-base.cc
+ 	(svrev_impl::expand): Use the new patterns for boolean svrev.
+ 
+ 2025-08-14  Richard Sandiford  <richard.sandiford@arm.com>
+ 
+ 	Backported from master:
+ 	2025-08-14  Richard Sandiford  <richard.sandiford@arm.com>
+ 
+ 	PR target/121294
+ 	* config/aarch64/iterators.md (UNSPEC_TRN1_CONV): Delete.
+ 	(UNSPEC_PERMUTE_PRED): New unspec.
+ 	* config/aarch64/aarch64-sve.md (@aarch64_sve_trn1_conv<mode>):
+ 	Replace with...
+ 	(@aarch64_sve_<perm_insn><mode>_acle)
+ 	(*aarch64_sve_<perm_insn><mode>_acle): ...these new patterns.
+ 	* config/aarch64/aarch64.cc (aarch64_expand_sve_const_pred_trn):
+ 	Update accordingly.
+ 	* config/aarch64/aarch64-sve-builtins-functions.h
+ 	(binary_permute::expand): Use the new _acle patterns for
+ 	predicate operations.
+ 
+ 2025-08-14  H.J. Lu  <hjl.tools@gmail.com>
+ 
+ 	Backported from master:
+ 	2025-07-28  H.J. Lu  <hjl.tools@gmail.com>
+ 
+ 	PR target/121208
+ 	* config/i386/i386.cc (ix86_tls_get_addr): Issue an error for
+ 	-mtls-dialect=gnu with no_caller_saved_registers attribute and
+ 	suggest -mtls-dialect=gnu2.
+ 
+ 2025-08-13  Lulu Cheng  <chenglulu@loongson.cn>
+ 
+ 	Backported from master:
+ 	2025-08-13  Lulu Cheng  <chenglulu@loongson.cn>
+ 
+ 	PR target/120476
+ 	* config/loongarch/loongarch.cc
+ 	(loongarch_compute_pressure_classes): New function.
+ 	(TARGET_COMPUTE_PRESSURE_CLASSES): Define.
+ 
+ 2025-08-12  mengqinggang  <mengqinggang@loongson.cn>
+ 
+ 	Backported from master:
+ 	2025-08-12  mengqinggang  <mengqinggang@loongson.cn>
+ 
+ 	* config/loongarch/loongarch-def.h (ABI_BASE_LP64D): New macro.
+ 	(ABI_BASE_LP64F): New macro.
+ 	(ABI_BASE_LP64S): New macro.
+ 	(N_ABI_BASE_TYPES): New macro.
+ 
+ 2025-08-08  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	Backported from master:
+ 	2025-08-06  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	PR tree-optimization/121413
+ 	* gimple-lower-bitint.cc (abi_limb_prec): New variable
+ 	(bitint_precision_kind): Initialize it.
+ 	(gimple_lower_bitint): Clear it at the start.  For
+ 	min_prec > limb_prec descreased precision vars for
+ 	INTEGER_CST PHI arguments ensure min_prec is either
+ 	prec or multiple of abi_limb_prec.
+ 
+ 2025-08-08  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	Backported from master:
+ 	2025-08-06  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	PR tree-optimization/121127
+ 	* gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr): For
+ 	uninitialized SSA_NAME, set *prec_stored to 0 rather than *prec.
+ 	Handle that case in narrowing casts.  If prec_stored is non-NULL,
+ 	set *prec_stored to prec_stored_val.
+ 
+ 2025-08-08  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	Backported from master:
+ 	2025-08-01  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	PR middle-end/121322
+ 	* gimple-ssa-store-merging.cc (find_bswap_or_nop): Return NULL if
+ 	count is 0.
+ 
  2025-07-31  Spencer Abson  <spencer.abson@arm.com>
  
  	Backported from master:
diff -Nrcpad gcc-14-20250808/gcc/DATESTAMP gcc-14-20250815/gcc/DATESTAMP
*** gcc-14-20250808/gcc/DATESTAMP	Fri Aug  8 22:32:31 2025
--- gcc-14-20250815/gcc/DATESTAMP	Fri Aug 15 22:32:06 2025
***************
*** 1 ****
! 20250808
--- 1 ----
! 20250815
diff -Nrcpad gcc-14-20250808/gcc/c-family/ChangeLog gcc-14-20250815/gcc/c-family/ChangeLog
*** gcc-14-20250808/gcc/c-family/ChangeLog	Fri Aug  8 22:32:41 2025
--- gcc-14-20250815/gcc/c-family/ChangeLog	Fri Aug 15 22:32:07 2025
***************
*** 1,3 ****
--- 1,14 ----
+ 2025-08-08  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	Backported from master:
+ 	2025-07-04  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	PR c/120837
+ 	* c-common.cc (pointer_int_sum): Rewrite the intop PLUS_EXPR or
+ 	MINUS_EXPR optimization into extension of both intop operands,
+ 	their separate multiplication and then addition/subtraction followed
+ 	by rest of pointer_int_sum handling after the multiplication.
+ 
  2025-05-23  Release Manager
  
  	* GCC 14.3.0 released.
diff -Nrcpad gcc-14-20250808/gcc/config/aarch64/aarch64-sve-builtins-base.cc gcc-14-20250815/gcc/config/aarch64/aarch64-sve-builtins-base.cc
*** gcc-14-20250808/gcc/config/aarch64/aarch64-sve-builtins-base.cc	Fri Aug  8 22:32:42 2025
--- gcc-14-20250815/gcc/config/aarch64/aarch64-sve-builtins-base.cc	Fri Aug 15 22:32:07 2025
*************** public:
*** 2396,2402 ****
    rtx
    expand (function_expander &e) const override
    {
!     return e.use_exact_insn (code_for_aarch64_sve_rev (e.vector_mode (0)));
    }
  };
  
--- 2396,2405 ----
    rtx
    expand (function_expander &e) const override
    {
!     auto mode = e.vector_mode (0);
!     return e.use_exact_insn (e.type_suffix (0).bool_p
! 			     ? code_for_aarch64_sve_rev_acle (mode)
! 			     : code_for_aarch64_sve_rev (mode));
    }
  };
  
diff -Nrcpad gcc-14-20250808/gcc/config/aarch64/aarch64-sve-builtins-functions.h gcc-14-20250815/gcc/config/aarch64/aarch64-sve-builtins-functions.h
*** gcc-14-20250808/gcc/config/aarch64/aarch64-sve-builtins-functions.h	Fri Aug  8 22:32:42 2025
--- gcc-14-20250815/gcc/config/aarch64/aarch64-sve-builtins-functions.h	Fri Aug 15 22:32:07 2025
*************** public:
*** 615,621 ****
    rtx
    expand (function_expander &e) const override
    {
!     insn_code icode = code_for_aarch64_sve (m_unspec, e.vector_mode (0));
      return e.use_exact_insn (icode);
    }
  
--- 615,624 ----
    rtx
    expand (function_expander &e) const override
    {
!     auto mode = e.vector_mode (0);
!     insn_code icode = (e.type_suffix (0).bool_p
! 		       ? code_for_aarch64_sve_acle (m_unspec, mode)
! 		       : code_for_aarch64_sve (m_unspec, mode));
      return e.use_exact_insn (icode);
    }
  
diff -Nrcpad gcc-14-20250808/gcc/config/aarch64/aarch64-sve.md gcc-14-20250815/gcc/config/aarch64/aarch64-sve.md
*** gcc-14-20250808/gcc/config/aarch64/aarch64-sve.md	Fri Aug  8 22:32:42 2025
--- gcc-14-20250815/gcc/config/aarch64/aarch64-sve.md	Fri Aug 15 22:32:07 2025
***************
*** 1458,1475 ****
  	  UNSPEC_LD1_GATHER))]
    "TARGET_SVE && TARGET_NON_STREAMING"
    {@ [cons: =0, 1, 2, 3, 4, 5  ]
!      [&w, Z,   w, Ui1, Ui1, Upl] ld1<Vesize>\t%0.s, %5/z, [%2.s]
!      [?w, Z,   0, Ui1, Ui1, Upl] ^
!      [&w, vgw, w, Ui1, Ui1, Upl] ld1<Vesize>\t%0.s, %5/z, [%2.s, #%1]
!      [?w, vgw, 0, Ui1, Ui1, Upl] ^
!      [&w, rk,  w, Z,   Ui1, Upl] ld1<Vesize>\t%0.s, %5/z, [%1, %2.s, sxtw]
!      [?w, rk,  0, Z,   Ui1, Upl] ^
!      [&w, rk,  w, Ui1, Ui1, Upl] ld1<Vesize>\t%0.s, %5/z, [%1, %2.s, uxtw]
!      [?w, rk,  0, Ui1, Ui1, Upl] ^
!      [&w, rk,  w, Z,   i,   Upl] ld1<Vesize>\t%0.s, %5/z, [%1, %2.s, sxtw %p4]
!      [?w, rk,  0, Z,   i,   Upl] ^
!      [&w, rk,  w, Ui1, i,   Upl] ld1<Vesize>\t%0.s, %5/z, [%1, %2.s, uxtw %p4]
!      [?w, rk,  0, Ui1, i,   Upl] ^
    }
  )
  
--- 1458,1475 ----
  	  UNSPEC_LD1_GATHER))]
    "TARGET_SVE && TARGET_NON_STREAMING"
    {@ [cons: =0, 1, 2, 3, 4, 5  ]
!      [&w, Z,          w, Ui1, Ui1, Upl] ld1<Vesize>\t%0.s, %5/z, [%2.s]
!      [?w, Z,          0, Ui1, Ui1, Upl] ^
!      [&w, vg<Vesize>, w, Ui1, Ui1, Upl] ld1<Vesize>\t%0.s, %5/z, [%2.s, #%1]
!      [?w, vg<Vesize>, 0, Ui1, Ui1, Upl] ^
!      [&w, rk,         w, Z,   Ui1, Upl] ld1<Vesize>\t%0.s, %5/z, [%1, %2.s, sxtw]
!      [?w, rk,         0, Z,   Ui1, Upl] ^
!      [&w, rk,         w, Ui1, Ui1, Upl] ld1<Vesize>\t%0.s, %5/z, [%1, %2.s, uxtw]
!      [?w, rk,         0, Ui1, Ui1, Upl] ^
!      [&w, rk,         w, Z,   i,   Upl] ld1<Vesize>\t%0.s, %5/z, [%1, %2.s, sxtw %p4]
!      [?w, rk,         0, Z,   i,   Upl] ^
!      [&w, rk,         w, Ui1, i,   Upl] ld1<Vesize>\t%0.s, %5/z, [%1, %2.s, uxtw %p4]
!      [?w, rk,         0, Ui1, i,   Upl] ^
    }
  )
  
***************
*** 1487,1500 ****
  	  UNSPEC_LD1_GATHER))]
    "TARGET_SVE && TARGET_NON_STREAMING"
    {@ [cons: =0, 1, 2, 3, 4, 5]
!      [&w, Z,   w, i, Ui1, Upl] ld1<Vesize>\t%0.d, %5/z, [%2.d]
!      [?w, Z,   0, i, Ui1, Upl] ^
!      [&w, vgd, w, i, Ui1, Upl] ld1<Vesize>\t%0.d, %5/z, [%2.d, #%1]
!      [?w, vgd, 0, i, Ui1, Upl] ^
!      [&w, rk,  w, i, Ui1, Upl] ld1<Vesize>\t%0.d, %5/z, [%1, %2.d]
!      [?w, rk,  0, i, Ui1, Upl] ^
!      [&w, rk,  w, i, i,   Upl] ld1<Vesize>\t%0.d, %5/z, [%1, %2.d, lsl %p4]
!      [?w, rk,  0, i, i,   Upl] ^
    }
  )
  
--- 1487,1500 ----
  	  UNSPEC_LD1_GATHER))]
    "TARGET_SVE && TARGET_NON_STREAMING"
    {@ [cons: =0, 1, 2, 3, 4, 5]
!      [&w, Z,          w, i, Ui1, Upl] ld1<Vesize>\t%0.d, %5/z, [%2.d]
!      [?w, Z,          0, i, Ui1, Upl] ^
!      [&w, vg<Vesize>, w, i, Ui1, Upl] ld1<Vesize>\t%0.d, %5/z, [%2.d, #%1]
!      [?w, vg<Vesize>, 0, i, Ui1, Upl] ^
!      [&w, rk,         w, i, Ui1, Upl] ld1<Vesize>\t%0.d, %5/z, [%1, %2.d]
!      [?w, rk,         0, i, Ui1, Upl] ^
!      [&w, rk,         w, i, i,   Upl] ld1<Vesize>\t%0.d, %5/z, [%1, %2.d, lsl %p4]
!      [?w, rk,         0, i, i,   Upl] ^
    }
  )
  
***************
*** 2378,2390 ****
  	   (match_operand:SVE_4 4 "register_operand")]
  	  UNSPEC_ST1_SCATTER))]
    "TARGET_SVE && TARGET_NON_STREAMING"
!   {@ [ cons: 0 , 1 , 2   , 3   , 4 , 5    ]
!      [ Z       , w , Ui1 , Ui1 , w , Upl  ] st1<Vesize>\t%4.s, %5, [%1.s]
!      [ vgw     , w , Ui1 , Ui1 , w , Upl  ] st1<Vesize>\t%4.s, %5, [%1.s, #%0]
!      [ rk      , w , Z   , Ui1 , w , Upl  ] st1<Vesize>\t%4.s, %5, [%0, %1.s, sxtw]
!      [ rk      , w , Ui1 , Ui1 , w , Upl  ] st1<Vesize>\t%4.s, %5, [%0, %1.s, uxtw]
!      [ rk      , w , Z   , i   , w , Upl  ] st1<Vesize>\t%4.s, %5, [%0, %1.s, sxtw %p3]
!      [ rk      , w , Ui1 , i   , w , Upl  ] st1<Vesize>\t%4.s, %5, [%0, %1.s, uxtw %p3]
    }
  )
  
--- 2378,2390 ----
  	   (match_operand:SVE_4 4 "register_operand")]
  	  UNSPEC_ST1_SCATTER))]
    "TARGET_SVE && TARGET_NON_STREAMING"
!   {@ [ cons: 0    , 1 , 2   , 3   , 4 , 5    ]
!      [ Z          , w , Ui1 , Ui1 , w , Upl  ] st1<Vesize>\t%4.s, %5, [%1.s]
!      [ vg<Vesize> , w , Ui1 , Ui1 , w , Upl  ] st1<Vesize>\t%4.s, %5, [%1.s, #%0]
!      [ rk         , w , Z   , Ui1 , w , Upl  ] st1<Vesize>\t%4.s, %5, [%0, %1.s, sxtw]
!      [ rk         , w , Ui1 , Ui1 , w , Upl  ] st1<Vesize>\t%4.s, %5, [%0, %1.s, uxtw]
!      [ rk         , w , Z   , i   , w , Upl  ] st1<Vesize>\t%4.s, %5, [%0, %1.s, sxtw %p3]
!      [ rk         , w , Ui1 , i   , w , Upl  ] st1<Vesize>\t%4.s, %5, [%0, %1.s, uxtw %p3]
    }
  )
  
***************
*** 2401,2411 ****
  	   (match_operand:SVE_2 4 "register_operand")]
  	  UNSPEC_ST1_SCATTER))]
    "TARGET_SVE && TARGET_NON_STREAMING"
!   {@ [ cons: 0 , 1 , 3   , 4 , 5    ]
!      [ Z       , w , Ui1 , w , Upl  ] st1<Vesize>\t%4.d, %5, [%1.d]
!      [ vgd     , w , Ui1 , w , Upl  ] st1<Vesize>\t%4.d, %5, [%1.d, #%0]
!      [ rk      , w , Ui1 , w , Upl  ] st1<Vesize>\t%4.d, %5, [%0, %1.d]
!      [ rk      , w , i   , w , Upl  ] st1<Vesize>\t%4.d, %5, [%0, %1.d, lsl %p3]
    }
  )
  
--- 2401,2411 ----
  	   (match_operand:SVE_2 4 "register_operand")]
  	  UNSPEC_ST1_SCATTER))]
    "TARGET_SVE && TARGET_NON_STREAMING"
!   {@ [ cons: 0    , 1 , 3   , 4 , 5    ]
!      [ Z          , w , Ui1 , w , Upl  ] st1<Vesize>\t%4.d, %5, [%1.d]
!      [ vg<Vesize> , w , Ui1 , w , Upl  ] st1<Vesize>\t%4.d, %5, [%1.d, #%0]
!      [ rk         , w , Ui1 , w , Upl  ] st1<Vesize>\t%4.d, %5, [%0, %1.d]
!      [ rk         , w , i   , w , Upl  ] st1<Vesize>\t%4.d, %5, [%0, %1.d, lsl %p3]
    }
  )
  
***************
*** 9123,9129 ****
  	(unspec:PRED_ALL [(match_operand:PRED_ALL 1 "register_operand" "Upa")]
  			 UNSPEC_REV))]
    "TARGET_SVE"
!   "rev\t%0.<Vetype>, %1.<Vetype>")
  
  ;; -------------------------------------------------------------------------
  ;; ---- [PRED] Special-purpose binary permutes
--- 9123,9152 ----
  	(unspec:PRED_ALL [(match_operand:PRED_ALL 1 "register_operand" "Upa")]
  			 UNSPEC_REV))]
    "TARGET_SVE"
!   "rev\t%0.<Vetype>, %1.<Vetype>"
! )
! 
! (define_expand "@aarch64_sve_rev<mode>_acle"
!   [(set (match_operand:VNx16BI 0 "register_operand")
! 	(unspec:VNx16BI
! 	  [(match_operand:VNx16BI 1 "register_operand")
! 	   (match_dup:PRED_ALL 2)]
! 	  UNSPEC_REV_PRED))]
!   "TARGET_SVE"
!   {
!     operands[2] = CONST0_RTX (<MODE>mode);
!   }
! )
! 
! (define_insn "*aarch64_sve_rev<mode>_acle"
!   [(set (match_operand:VNx16BI 0 "register_operand" "=Upa")
! 	(unspec:VNx16BI
! 	  [(match_operand:VNx16BI 1 "register_operand" "Upa")
! 	   (match_operand:PRED_ALL 2 "aarch64_simd_imm_zero")]
! 	  UNSPEC_REV_PRED))]
!   "TARGET_SVE"
!   "rev\t%0.<Vetype>, %1.<Vetype>"
! )
  
  ;; -------------------------------------------------------------------------
  ;; ---- [PRED] Special-purpose binary permutes
***************
*** 9148,9165 ****
    "<perm_insn>\t%0.<Vetype>, %1.<Vetype>, %2.<Vetype>"
  )
  
! ;; Special purpose permute used by the predicate generation instructions.
! ;; Unlike the normal permute patterns, these instructions operate on VNx16BI
! ;; regardless of the element size, so that all input and output bits are
! ;; well-defined.  Operand 3 then indicates the size of the permute.
! (define_insn "@aarch64_sve_trn1_conv<mode>"
    [(set (match_operand:VNx16BI 0 "register_operand" "=Upa")
  	(unspec:VNx16BI [(match_operand:VNx16BI 1 "register_operand" "Upa")
  			 (match_operand:VNx16BI 2 "register_operand" "Upa")
! 			 (match_operand:PRED_ALL 3 "aarch64_simd_imm_zero")]
! 			UNSPEC_TRN1_CONV))]
    "TARGET_SVE"
!   "trn1\t%0.<PRED_ALL:Vetype>, %1.<PRED_ALL:Vetype>, %2.<PRED_ALL:Vetype>"
  )
  
  ;; =========================================================================
--- 9171,9209 ----
    "<perm_insn>\t%0.<Vetype>, %1.<Vetype>, %2.<Vetype>"
  )
  
! ;; Special-purpose permutes used by the ACLE intrinsics and predicate
! ;; generation instructions.  Unlike the normal permute patterns, these
! ;; instructions operate on VNx16BI regardless of the element size, so that
! ;; all input and output bits are well-defined.  Operand 3 then indicates
! ;; the size of the permute.
! ;;
! ;; To make generation easier, this pattern embeds the permute type as the
! ;; fourth operand to the unspec.  On the one hand, this avoids overloading
! ;; unspecs like UNSPEC_ZIP1 to represent two different operations.  On the
! ;; other hand, it avoids having a separate unspec for each variant, and
! ;; having to map from one kind of unspec to the other.
! (define_expand "@aarch64_sve_<perm_insn><mode>_acle"
!   [(set (match_operand:VNx16BI 0 "register_operand")
! 	(unspec:VNx16BI [(match_operand:VNx16BI 1 "register_operand")
! 			 (match_operand:VNx16BI 2 "register_operand")
! 			 (match_dup:PRED_ALL 3)
! 			 (const_int PERMUTE)]
! 			UNSPEC_PERMUTE_PRED))]
!   "TARGET_SVE"
!   {
!     operands[3] = CONST0_RTX (<MODE>mode);
!   }
! )
! 
! (define_insn "*aarch64_sve_<perm_insn><mode>_acle"
    [(set (match_operand:VNx16BI 0 "register_operand" "=Upa")
  	(unspec:VNx16BI [(match_operand:VNx16BI 1 "register_operand" "Upa")
  			 (match_operand:VNx16BI 2 "register_operand" "Upa")
! 			 (match_operand:PRED_ALL 3 "aarch64_simd_imm_zero")
! 			 (const_int PERMUTE)]
! 			UNSPEC_PERMUTE_PRED))]
    "TARGET_SVE"
!   "<perm_insn>\t%0.<PRED_ALL:Vetype>, %1.<PRED_ALL:Vetype>, %2.<PRED_ALL:Vetype>"
  )
  
  ;; =========================================================================
diff -Nrcpad gcc-14-20250808/gcc/config/aarch64/aarch64.cc gcc-14-20250815/gcc/config/aarch64/aarch64.cc
*** gcc-14-20250808/gcc/config/aarch64/aarch64.cc	Fri Aug  8 22:32:42 2025
--- gcc-14-20250815/gcc/config/aarch64/aarch64.cc	Fri Aug 15 22:32:07 2025
*************** aarch64_expand_sve_const_pred_trn (rtx t
*** 5824,5831 ****
       operands but permutes them as though they had mode MODE.  */
    machine_mode mode = aarch64_sve_pred_mode (permute_size).require ();
    target = aarch64_target_reg (target, GET_MODE (a));
!   rtx type_reg = CONST0_RTX (mode);
!   emit_insn (gen_aarch64_sve_trn1_conv (mode, target, a, b, type_reg));
    return target;
  }
  
--- 5824,5830 ----
       operands but permutes them as though they had mode MODE.  */
    machine_mode mode = aarch64_sve_pred_mode (permute_size).require ();
    target = aarch64_target_reg (target, GET_MODE (a));
!   emit_insn (gen_aarch64_sve_acle (UNSPEC_TRN1, mode, target, a, b));
    return target;
  }
  
*************** aarch64_asm_preferred_eh_data_format (in
*** 24439,24458 ****
     return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type;
  }
  
  /* Output .variant_pcs for aarch64_vector_pcs function symbols.  */
  
  static void
  aarch64_asm_output_variant_pcs (FILE *stream, const tree decl, const char* name)
  {
!   if (TREE_CODE (decl) == FUNCTION_DECL)
      {
!       arm_pcs pcs = (arm_pcs) fndecl_abi (decl).id ();
!       if (pcs == ARM_PCS_SIMD || pcs == ARM_PCS_SVE)
! 	{
! 	  fprintf (stream, "\t.variant_pcs\t");
! 	  assemble_name (stream, name);
! 	  fprintf (stream, "\n");
! 	}
      }
  }
  
--- 24438,24478 ----
     return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type;
  }
  
+ /* Return true if function declaration FNDECL needs to be marked as
+    having a variant PCS.  */
+ 
+ static bool
+ aarch64_is_variant_pcs (tree fndecl)
+ {
+   /* Check for ABIs that preserve more registers than usual.  */
+   arm_pcs pcs = (arm_pcs) fndecl_abi (fndecl).id ();
+   if (pcs == ARM_PCS_SIMD || pcs == ARM_PCS_SVE)
+     return true;
+ 
+   /* Check for ABIs that allow PSTATE.SM to be 1 on entry.  */
+   tree fntype = TREE_TYPE (fndecl);
+   if (aarch64_fntype_pstate_sm (fntype) != AARCH64_FL_SM_OFF)
+     return true;
+ 
+   /* Check for ABIs that require PSTATE.ZA to be 1 on entry, either because
+      of ZA or ZT0.  */
+   if (aarch64_fntype_pstate_za (fntype) != 0)
+     return true;
+ 
+   return false;
+ }
+ 
  /* Output .variant_pcs for aarch64_vector_pcs function symbols.  */
  
  static void
  aarch64_asm_output_variant_pcs (FILE *stream, const tree decl, const char* name)
  {
!   if (TREE_CODE (decl) == FUNCTION_DECL
!       && aarch64_is_variant_pcs (decl))
      {
!       fprintf (stream, "\t.variant_pcs\t");
!       assemble_name (stream, name);
!       fprintf (stream, "\n");
      }
  }
  
diff -Nrcpad gcc-14-20250808/gcc/config/aarch64/aarch64.md gcc-14-20250815/gcc/config/aarch64/aarch64.md
*** gcc-14-20250808/gcc/config/aarch64/aarch64.md	Fri Aug  8 22:32:42 2025
--- gcc-14-20250815/gcc/config/aarch64/aarch64.md	Fri Aug 15 22:32:07 2025
***************
*** 267,272 ****
--- 267,273 ----
      UNSPEC_PACIBSP
      UNSPEC_PRLG_STK
      UNSPEC_REV
+     UNSPEC_REV_PRED
      UNSPEC_RBIT
      UNSPEC_SADALP
      UNSPEC_SCVTF
diff -Nrcpad gcc-14-20250808/gcc/config/aarch64/iterators.md gcc-14-20250815/gcc/config/aarch64/iterators.md
*** gcc-14-20250808/gcc/config/aarch64/iterators.md	Fri Aug  8 22:32:42 2025
--- gcc-14-20250815/gcc/config/aarch64/iterators.md	Fri Aug 15 22:32:07 2025
***************
*** 823,829 ****
      UNSPEC_UZP2Q	; Used in aarch64-sve.md.
      UNSPEC_ZIP1Q	; Used in aarch64-sve.md.
      UNSPEC_ZIP2Q	; Used in aarch64-sve.md.
-     UNSPEC_TRN1_CONV	; Used in aarch64-sve.md.
      UNSPEC_COND_CMPEQ_WIDE ; Used in aarch64-sve.md.
      UNSPEC_COND_CMPGE_WIDE ; Used in aarch64-sve.md.
      UNSPEC_COND_CMPGT_WIDE ; Used in aarch64-sve.md.
--- 823,828 ----
***************
*** 1053,1058 ****
--- 1052,1060 ----
      UNSPEC_BFCVT       ; Used in aarch64-simd.md.
      UNSPEC_FCVTXN	; Used in aarch64-simd.md.
  
+     ;; All used in aarch64-sve.md
+     UNSPEC_PERMUTE_PRED
+ 
      ;; All used in aarch64-sve2.md
      UNSPEC_FCVTN
      UNSPEC_FDOT
diff -Nrcpad gcc-14-20250808/gcc/config/i386/i386.cc gcc-14-20250815/gcc/config/i386/i386.cc
*** gcc-14-20250808/gcc/config/i386/i386.cc	Fri Aug  8 22:32:42 2025
--- gcc-14-20250815/gcc/config/i386/i386.cc	Fri Aug 15 22:32:07 2025
*************** static GTY(()) rtx ix86_tls_symbol;
*** 12119,12124 ****
--- 12119,12146 ----
  static rtx
  ix86_tls_get_addr (void)
  {
+   if (cfun->machine->call_saved_registers
+       == TYPE_NO_CALLER_SAVED_REGISTERS)
+     {
+       /* __tls_get_addr doesn't preserve vector registers.  When a
+ 	 function with no_caller_saved_registers attribute calls
+ 	 __tls_get_addr, YMM and ZMM registers will be clobbered.
+ 	 Issue an error and suggest -mtls-dialect=gnu2 in this case.  */
+       if (cfun->machine->func_type == TYPE_NORMAL)
+ 	error (G_("%<-mtls-dialect=gnu2%> must be used with a function"
+ 		  " with the %<no_caller_saved_registers%> attribute"));
+       else
+ 	error (cfun->machine->func_type == TYPE_EXCEPTION
+ 	       ? G_("%<-mtls-dialect=gnu2%> must be used with an"
+ 		    " exception service routine")
+ 	       : G_("%<-mtls-dialect=gnu2%> must be used with an"
+ 		    " interrupt service routine"));
+       /* Don't issue the same error twice.  */
+       cfun->machine->func_type = TYPE_NORMAL;
+       cfun->machine->call_saved_registers
+ 	= TYPE_DEFAULT_CALL_SAVED_REGISTERS;
+     }
+ 
    if (!ix86_tls_symbol)
      {
        const char *sym
diff -Nrcpad gcc-14-20250808/gcc/config/loongarch/loongarch-def.h gcc-14-20250815/gcc/config/loongarch/loongarch-def.h
*** gcc-14-20250808/gcc/config/loongarch/loongarch-def.h	Fri Aug  8 22:32:42 2025
--- gcc-14-20250815/gcc/config/loongarch/loongarch-def.h	Fri Aug 15 22:32:07 2025
*************** extern loongarch_def_array<const char *,
*** 78,89 ****
  
  
  /* Base ABI */
! enum {
!   ABI_BASE_LP64D	= 0,
!   ABI_BASE_LP64F	= 1,
!   ABI_BASE_LP64S	= 2,
!   N_ABI_BASE_TYPES	= 3
! };
  
  extern loongarch_def_array<const char *, N_ABI_BASE_TYPES>
    loongarch_abi_base_strings;
--- 78,87 ----
  
  
  /* Base ABI */
! #define ABI_BASE_LP64D	  0
! #define ABI_BASE_LP64F	  1
! #define ABI_BASE_LP64S	  2
! #define N_ABI_BASE_TYPES  3
  
  extern loongarch_def_array<const char *, N_ABI_BASE_TYPES>
    loongarch_abi_base_strings;
diff -Nrcpad gcc-14-20250808/gcc/config/loongarch/loongarch.cc gcc-14-20250815/gcc/config/loongarch/loongarch.cc
*** gcc-14-20250808/gcc/config/loongarch/loongarch.cc	Fri Aug  8 22:32:42 2025
--- gcc-14-20250815/gcc/config/loongarch/loongarch.cc	Fri Aug 15 22:32:07 2025
*************** loongarch_vector_costs::add_stmt_cost (i
*** 4280,4285 ****
--- 4280,4286 ----
  	    break;
  	  }
        else if (TARGET_RECIP_VEC_DIV
+ 	       && vectype
  	       && gimple_code (stmt_info->stmt) == GIMPLE_ASSIGN)
  	{
  	  machine_mode mode = TYPE_MODE (vectype);
*************** loongarch_c_mode_for_suffix (char suffix
*** 10950,10955 ****
--- 10951,10968 ----
    return VOIDmode;
  }
  
+ /* Implement TARGET_COMPUTE_PRESSURE_CLASSES.  */
+ 
+ static int
+ loongarch_compute_pressure_classes (reg_class *classes)
+ {
+   int i = 0;
+   classes[i++] = GENERAL_REGS;
+   classes[i++] = FP_REGS;
+   classes[i++] = FCC_REGS;
+   return i;
+ }
+ 
  /* Initialize the GCC target structure.  */
  #undef TARGET_ASM_ALIGNED_HI_OP
  #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
*************** loongarch_c_mode_for_suffix (char suffix
*** 11212,11217 ****
--- 11225,11233 ----
  #undef TARGET_C_MODE_FOR_SUFFIX
  #define TARGET_C_MODE_FOR_SUFFIX loongarch_c_mode_for_suffix
  
+ #undef TARGET_COMPUTE_PRESSURE_CLASSES
+ #define TARGET_COMPUTE_PRESSURE_CLASSES loongarch_compute_pressure_classes
+ 
  struct gcc_target targetm = TARGET_INITIALIZER;
  
  #include "gt-loongarch.h"
diff -Nrcpad gcc-14-20250808/gcc/cp/ChangeLog gcc-14-20250815/gcc/cp/ChangeLog
*** gcc-14-20250808/gcc/cp/ChangeLog	Fri Aug  8 22:32:42 2025
--- gcc-14-20250815/gcc/cp/ChangeLog	Fri Aug 15 22:32:08 2025
***************
*** 1,3 ****
--- 1,12 ----
+ 2025-08-08  Patrick Palka  <ppalka@redhat.com>
+ 
+ 	Backported from master:
+ 	2025-08-04  Patrick Palka  <ppalka@redhat.com>
+ 
+ 	PR c++/120620
+ 	* constexpr.cc (cxx_dynamic_cast_fn_p): Return true only
+ 	for synthesized __dynamic_cast.
+ 
  2025-08-01  Jason Merrill  <jason@redhat.com>
  
  	Backported from master:
diff -Nrcpad gcc-14-20250808/gcc/doc/sourcebuild.texi gcc-14-20250815/gcc/doc/sourcebuild.texi
*** gcc-14-20250808/gcc/doc/sourcebuild.texi	Fri Aug  8 22:32:43 2025
--- gcc-14-20250815/gcc/doc/sourcebuild.texi	Fri Aug 15 22:32:08 2025
*************** whether it does so by default).
*** 2346,2351 ****
--- 2346,2354 ----
  @itemx aarch64_sve1024_hw
  @itemx aarch64_sve2048_hw
  Like @code{aarch64_sve_hw}, but also test for an exact hardware vector length.
+ @item aarch64_sme_hw
+ AArch64 target that is able to generate and execute SME code (regardless of
+ whether it does so by default).
  
  @item aarch64_fjcvtzs_hw
  AArch64 target that is able to generate and execute armv8.3-a FJCVTZS
diff -Nrcpad gcc-14-20250808/gcc/testsuite/ChangeLog gcc-14-20250815/gcc/testsuite/ChangeLog
*** gcc-14-20250808/gcc/testsuite/ChangeLog	Fri Aug  8 22:32:44 2025
--- gcc-14-20250815/gcc/testsuite/ChangeLog	Fri Aug 15 22:32:09 2025
***************
*** 1,3 ****
--- 1,130 ----
+ 2025-08-14  Richard Sandiford  <richard.sandiford@arm.com>
+ 
+ 	Backported from master:
+ 	2025-08-14  Richard Sandiford  <richard.sandiford@arm.com>
+ 
+ 	PR target/121414
+ 	* gcc.target/aarch64/sme/pr121414_1.c: New test.
+ 
+ 2025-08-14  Richard Sandiford  <richard.sandiford@arm.com>
+ 
+ 	Backported from master:
+ 	2025-08-14  Richard Sandiford  <richard.sandiford@arm.com>
+ 
+ 	PR target/121294
+ 	* gcc.target/aarch64/sve/acle/general/rev_2.c: New test.
+ 
+ 2025-08-14  Richard Sandiford  <richard.sandiford@arm.com>
+ 
+ 	Backported from master:
+ 	2025-08-14  Richard Sandiford  <richard.sandiford@arm.com>
+ 
+ 	PR target/121294
+ 	* gcc.target/aarch64/sve/acle/general/perm_2.c: New test.
+ 	* gcc.target/aarch64/sve/acle/general/perm_3.c: Likewise.
+ 	* gcc.target/aarch64/sve/acle/general/perm_4.c: Likewise.
+ 	* gcc.target/aarch64/sve/acle/general/perm_5.c: Likewise.
+ 	* gcc.target/aarch64/sve/acle/general/perm_6.c: Likewise.
+ 	* gcc.target/aarch64/sve/acle/general/perm_7.c: Likewise.
+ 
+ 2025-08-14  H.J. Lu  <hjl.tools@gmail.com>
+ 
+ 	Backported from master:
+ 	2025-07-29  H.J. Lu  <hjl.tools@gmail.com>
+ 
+ 	PR target/121208
+ 	* gcc.target/i386/pr121208-1a.c (dg-options): Add
+ 	-mno-sse -mno-mmx -mno-80387.
+ 	* gcc.target/i386/pr121208-1b.c (dg-options): Likewise.
+ 
+ 2025-08-14  H.J. Lu  <hjl.tools@gmail.com>
+ 
+ 	Backported from master:
+ 	2025-07-28  H.J. Lu  <hjl.tools@gmail.com>
+ 
+ 	PR target/121208
+ 	* gcc.target/i386/pr121208-1a.c: New test.
+ 	* gcc.target/i386/pr121208-1b.c: Likewise.
+ 	* gcc.target/i386/pr121208-2a.c: Likewise.
+ 	* gcc.target/i386/pr121208-2b.c: Likewise.
+ 	* gcc.target/i386/pr121208-3a.c: Likewise.
+ 	* gcc.target/i386/pr121208-3b.c: Likewise.
+ 
+ 2025-08-11  Alexandre Oliva  <oliva@adacore.com>
+ 
+ 	Backported from master:
+ 	2025-05-21  Alexandre Oliva  <oliva@adacore.com>
+ 
+ 	* gcc.dg/vect/tsvc/vect-tsvc-s332.c: Require vect_early_break_hw.
+ 	* gcc.dg/vect/tsvc/vect-tsvc-s481.c: Likewise.
+ 	* gcc.dg/vect/tsvc/vect-tsvc-s482.c: Likewise.
+ 
+ 2025-08-10  Torbjörn SVENSSON  <torbjorn.svensson@foss.st.com>
+ 
+ 	Backported from master:
+ 	2025-08-10  Torbjörn SVENSSON  <torbjorn.svensson@foss.st.com>
+ 
+ 	* lib/multiline.exp: Added pruning of .exe.
+ 
+ 2025-08-08  Patrick Palka  <ppalka@redhat.com>
+ 
+ 	Backported from master:
+ 	2025-08-04  Patrick Palka  <ppalka@redhat.com>
+ 
+ 	PR c++/120620
+ 	* g++.dg/cpp2a/constexpr-dynamic19.C: New test.
+ 	* g++.dg/cpp2a/constexpr-dynamic1a.C: New test.
+ 
+ 2025-08-08  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	Backported from master:
+ 	2025-08-06  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	PR tree-optimization/121413
+ 	* gcc.dg/torture/bitint-85.c: New test.
+ 
+ 2025-08-08  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	Backported from master:
+ 	2025-08-06  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	PR tree-optimization/121127
+ 	* gcc.dg/bitint-125.c: New test.
+ 
+ 2025-08-08  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	Backported from master:
+ 	2025-08-01  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	PR middle-end/121322
+ 	* gcc.dg/pr121322.c: New test.
+ 
+ 2025-08-08  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	Backported from master:
+ 	2025-07-11  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	PR c++/120954
+ 	* c-c++-common/Warray-bounds-11.c: New test.
+ 
+ 2025-08-08  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	Backported from master:
+ 	2025-07-04  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	PR c/120837
+ 	* gcc.dg/ubsan/pr120837.c: New test.
+ 
+ 2025-08-08  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	Backported from master:
+ 	2025-07-01  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	PR testsuite/120919
+ 	* gcc.target/powerpc/builtin_altivec_tr_stxvr_runnable.c (main): Change
+ 	sc, ss, si and sll vars from scalars to arrays of 2 elements,
+ 	initialize and test just the first one though.
+ 
  2025-08-01  Jason Merrill  <jason@redhat.com>
  
  	Backported from master:
diff -Nrcpad gcc-14-20250808/gcc/testsuite/g++.target/aarch64/sme/sme_throw_1.C gcc-14-20250815/gcc/testsuite/g++.target/aarch64/sme/sme_throw_1.C
*** gcc-14-20250808/gcc/testsuite/g++.target/aarch64/sme/sme_throw_1.C	Thu Jan  1 00:00:00 1970
--- gcc-14-20250815/gcc/testsuite/g++.target/aarch64/sme/sme_throw_1.C	Fri Aug 15 22:32:13 2025
***************
*** 0 ****
--- 1,56 ----
+ /* { dg-do run { target { aarch64*-linux-gnu* && aarch64_sme_hw } } } */
+ /* { dg-options "-fnon-call-exceptions" } */
+ 
+ #include <signal.h>
+ #include <arm_sme.h>
+ 
+ static bool caught;
+ 
+ [[gnu::noipa]] void thrower(int)
+ {
+   throw 1;
+ }
+ 
+ [[gnu::noipa]] void bar()
+ {
+   *(volatile int *)0 = 0;
+ }
+ 
+ [[gnu::noipa]] void foo()
+ {
+   try
+     {
+       bar();
+     }
+   catch (int)
+     {
+       caught = true;
+     }
+ }
+ 
+ __arm_new("za") __arm_locally_streaming void sme_user()
+ {
+   svbool_t all = svptrue_b8();
+   for (unsigned int i = 0; i < svcntb(); ++i)
+     {
+       svint8_t expected = svindex_s8(i + 1, i);
+       svwrite_hor_za8_m(0, i, all, expected);
+     }
+   foo();
+   for (unsigned int i = 0; i < svcntb(); ++i)
+     {
+       svint8_t expected = svindex_s8(i + 1, i);
+       svint8_t actual = svread_hor_za8_m(svdup_s8(0), all, 0, i);
+       if (svptest_any(all, svcmpne(all, expected, actual)))
+ 	__builtin_abort();
+     }
+   if (!caught)
+     __builtin_abort();
+ }
+ 
+ int main()
+ {
+   signal(SIGSEGV, thrower);
+   sme_user();
+   return 0;
+ }
diff -Nrcpad gcc-14-20250808/gcc/testsuite/g++.target/aarch64/sme/sme_throw_2.C gcc-14-20250815/gcc/testsuite/g++.target/aarch64/sme/sme_throw_2.C
*** gcc-14-20250808/gcc/testsuite/g++.target/aarch64/sme/sme_throw_2.C	Thu Jan  1 00:00:00 1970
--- gcc-14-20250815/gcc/testsuite/g++.target/aarch64/sme/sme_throw_2.C	Fri Aug 15 22:32:13 2025
***************
*** 0 ****
--- 1,4 ----
+ /* { dg-do run { target { aarch64*-linux-gnu* && aarch64_sme_hw } } } */
+ /* { dg-options "-O2 -fnon-call-exceptions" } */
+ 
+ #include "sme_throw_1.C"
diff -Nrcpad gcc-14-20250808/gcc/testsuite/g++.target/aarch64/sve/pr121449.C gcc-14-20250815/gcc/testsuite/g++.target/aarch64/sve/pr121449.C
*** gcc-14-20250808/gcc/testsuite/g++.target/aarch64/sve/pr121449.C	Thu Jan  1 00:00:00 1970
--- gcc-14-20250815/gcc/testsuite/g++.target/aarch64/sve/pr121449.C	Fri Aug 15 22:32:13 2025
***************
*** 0 ****
--- 1,44 ----
+ /* PR target/121449 */
+ /* { dg-do assemble { target aarch64_asm_sve_ok } } */
+ /* { dg-options "-O3 -save-temps" } */
+ 
+ struct example;
+ 
+ struct array {
+   unsigned length();
+   example *operator[](unsigned i) {
+     example **data = reinterpret_cast<example **>(this);
+     return data[i];
+   }
+ };
+ 
+ struct example {
+   int a[16];
+   bool is_even;
+   int version;
+   int count() { return is_even ? 2 : 1; }
+   void fun1(int, long);
+   void fun2(unsigned, unsigned);
+   void process(array &, array &);
+ };
+ 
+ bool found;
+ 
+ void example::process(array &a, array &b) {
+   for (unsigned i = 1; a.length(); i++) {
+     long total = 0;
+     for (unsigned k = 0; k <= i; k++) {
+       total += a[k]->count();
+     }
+     for (unsigned j = 0; j < i; j++) {
+       int major = b[j]->version;
+       if (found)
+         major += i;
+       fun1(i + 1, total);
+       fun2(j, major);
+     }
+   }
+ }
+ 
+ /* { dg-final { scan-assembler-not {\tld1b\t(z[0-9]+)\.d, p[0-7]/z, \[(z[0-9]+)\.d, #64\]} } } */
+ 
diff -Nrcpad gcc-14-20250808/gcc/testsuite/gcc.dg/vect/tsvc/vect-tsvc-s332.c gcc-14-20250815/gcc/testsuite/gcc.dg/vect/tsvc/vect-tsvc-s332.c
*** gcc-14-20250808/gcc/testsuite/gcc.dg/vect/tsvc/vect-tsvc-s332.c	Fri Aug  8 22:33:16 2025
--- gcc-14-20250815/gcc/testsuite/gcc.dg/vect/tsvc/vect-tsvc-s332.c	Fri Aug 15 22:32:15 2025
***************
*** 3,8 ****
--- 3,9 ----
  
  /* { dg-additional-options "--param vect-epilogues-nomask=0" } */
  /* { dg-require-effective-target vect_float } */
+ /* { dg-require-effective-target vect_early_break_hw } */
  /* { dg-add-options vect_early_break } */
  
  #include "tsvc.h"
diff -Nrcpad gcc-14-20250808/gcc/testsuite/gcc.dg/vect/tsvc/vect-tsvc-s481.c gcc-14-20250815/gcc/testsuite/gcc.dg/vect/tsvc/vect-tsvc-s481.c
*** gcc-14-20250808/gcc/testsuite/gcc.dg/vect/tsvc/vect-tsvc-s481.c	Fri Aug  8 22:33:16 2025
--- gcc-14-20250815/gcc/testsuite/gcc.dg/vect/tsvc/vect-tsvc-s481.c	Fri Aug 15 22:32:15 2025
***************
*** 3,8 ****
--- 3,9 ----
  
  /* { dg-additional-options "--param vect-epilogues-nomask=0" } */
  /* { dg-require-effective-target vect_float } */
+ /* { dg-require-effective-target vect_early_break_hw } */
  /* { dg-add-options vect_early_break } */
  
  #include "tsvc.h"
diff -Nrcpad gcc-14-20250808/gcc/testsuite/gcc.dg/vect/tsvc/vect-tsvc-s482.c gcc-14-20250815/gcc/testsuite/gcc.dg/vect/tsvc/vect-tsvc-s482.c
*** gcc-14-20250808/gcc/testsuite/gcc.dg/vect/tsvc/vect-tsvc-s482.c	Fri Aug  8 22:33:16 2025
--- gcc-14-20250815/gcc/testsuite/gcc.dg/vect/tsvc/vect-tsvc-s482.c	Fri Aug 15 22:32:15 2025
***************
*** 3,8 ****
--- 3,9 ----
  
  /* { dg-additional-options "--param vect-epilogues-nomask=0" } */
  /* { dg-require-effective-target vect_float } */
+ /* { dg-require-effective-target vect_early_break_hw } */
  /* { dg-add-options vect_early_break } */
  
  #include "tsvc.h"
diff -Nrcpad gcc-14-20250808/gcc/testsuite/gcc.target/aarch64/sme/pr121414_1.c gcc-14-20250815/gcc/testsuite/gcc.target/aarch64/sme/pr121414_1.c
*** gcc-14-20250808/gcc/testsuite/gcc.target/aarch64/sme/pr121414_1.c	Thu Jan  1 00:00:00 1970
--- gcc-14-20250815/gcc/testsuite/gcc.target/aarch64/sme/pr121414_1.c	Fri Aug 15 22:32:16 2025
***************
*** 0 ****
--- 1,27 ----
+ #pragma GCC target "+sme2"
+ 
+ void f1() __arm_streaming_compatible {}
+ void f2() __arm_streaming {}
+ void f3() __arm_in("za") {}
+ void f4() __arm_out("za") {}
+ void f5() __arm_inout("za") {}
+ void f6() __arm_in("zt0") {}
+ void f7() __arm_out("zt0") {}
+ void f8() __arm_inout("zt0") {}
+ 
+ __arm_locally_streaming void g1() {}
+ __arm_new("za") void g2() {}
+ __arm_new("zt0") void g3() {}
+ 
+ /* { dg-final { scan-assembler {\t\.variant_pcs\tf1\n} } } */
+ /* { dg-final { scan-assembler {\t\.variant_pcs\tf2\n} } } */
+ /* { dg-final { scan-assembler {\t\.variant_pcs\tf3\n} } } */
+ /* { dg-final { scan-assembler {\t\.variant_pcs\tf4\n} } } */
+ /* { dg-final { scan-assembler {\t\.variant_pcs\tf5\n} } } */
+ /* { dg-final { scan-assembler {\t\.variant_pcs\tf6\n} } } */
+ /* { dg-final { scan-assembler {\t\.variant_pcs\tf7\n} } } */
+ /* { dg-final { scan-assembler {\t\.variant_pcs\tf8\n} } } */
+ 
+ /* { dg-final { scan-assembler-not {\t\.variant_pcs\tg1\n} } } */
+ /* { dg-final { scan-assembler-not {\t\.variant_pcs\tg2\n} } } */
+ /* { dg-final { scan-assembler-not {\t\.variant_pcs\tg3\n} } } */
diff -Nrcpad gcc-14-20250808/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_2.c gcc-14-20250815/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_2.c
*** gcc-14-20250808/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_2.c	Thu Jan  1 00:00:00 1970
--- gcc-14-20250815/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_2.c	Fri Aug 15 22:32:16 2025
***************
*** 0 ****
--- 1,96 ----
+ /* { dg-options "-O2" } */
+ /* { dg-final { check-function-bodies "**" "" } } */
+ 
+ #include <arm_sve.h>
+ 
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
+ 
+ /*
+ ** test1:
+ **	...
+ **	ptrue	(p[0-3])\.h, all
+ **	...
+ **	trn1	p0\.h, p[0-3]\.h, \1\.h
+ **	ret
+ */
+ svbool_t
+ test1 ()
+ {
+   return svtrn1_b16 (svptrue_b8 (), svptrue_b16 ());
+ }
+ 
+ /*
+ ** test2:
+ **	...
+ **	ptrue	(p[0-3])\.h, all
+ **	...
+ **	trn1	p0\.h, \1\.h, p[0-3]\.h
+ **	ret
+ */
+ svbool_t
+ test2 ()
+ {
+   return svtrn1_b16 (svptrue_b16 (), svptrue_b8 ());
+ }
+ 
+ /*
+ ** test3:
+ **	...
+ **	ptrue	(p[0-3])\.s, all
+ **	...
+ **	trn1	p0\.s, p[0-3]\.s, \1\.s
+ **	ret
+ */
+ svbool_t
+ test3 ()
+ {
+   return svtrn1_b32 (svptrue_b8 (), svptrue_b32 ());
+ }
+ 
+ /*
+ ** test4:
+ **	...
+ **	ptrue	(p[0-3])\.s, all
+ **	...
+ **	trn1	p0\.s, \1\.s, p[0-3]\.s
+ **	ret
+ */
+ svbool_t
+ test4 ()
+ {
+   return svtrn1_b32 (svptrue_b32 (), svptrue_b8 ());
+ }
+ 
+ /*
+ ** test5:
+ **	...
+ **	ptrue	(p[0-3])\.d, all
+ **	...
+ **	trn1	p0\.d, p[0-3]\.d, \1\.d
+ **	ret
+ */
+ svbool_t
+ test5 ()
+ {
+   return svtrn1_b64 (svptrue_b8 (), svptrue_b64 ());
+ }
+ 
+ /*
+ ** test6:
+ **	...
+ **	ptrue	(p[0-3])\.d, all
+ **	...
+ **	trn1	p0\.d, \1\.d, p[0-3]\.d
+ **	ret
+ */
+ svbool_t
+ test6 ()
+ {
+   return svtrn1_b64 (svptrue_b64 (), svptrue_b8 ());
+ }
+ 
+ #ifdef __cplusplus
+ }
+ #endif
diff -Nrcpad gcc-14-20250808/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_3.c gcc-14-20250815/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_3.c
*** gcc-14-20250808/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_3.c	Thu Jan  1 00:00:00 1970
--- gcc-14-20250815/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_3.c	Fri Aug 15 22:32:16 2025
***************
*** 0 ****
--- 1,96 ----
+ /* { dg-options "-O2" } */
+ /* { dg-final { check-function-bodies "**" "" } } */
+ 
+ #include <arm_sve.h>
+ 
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
+ 
+ /*
+ ** test1:
+ **	...
+ **	ptrue	(p[0-3])\.h, all
+ **	...
+ **	trn2	p0\.h, p[0-3]\.h, \1\.h
+ **	ret
+ */
+ svbool_t
+ test1 ()
+ {
+   return svtrn2_b16 (svptrue_b8 (), svptrue_b16 ());
+ }
+ 
+ /*
+ ** test2:
+ **	...
+ **	ptrue	(p[0-3])\.h, all
+ **	...
+ **	trn2	p0\.h, \1\.h, p[0-3]\.h
+ **	ret
+ */
+ svbool_t
+ test2 ()
+ {
+   return svtrn2_b16 (svptrue_b16 (), svptrue_b8 ());
+ }
+ 
+ /*
+ ** test3:
+ **	...
+ **	ptrue	(p[0-3])\.s, all
+ **	...
+ **	trn2	p0\.s, p[0-3]\.s, \1\.s
+ **	ret
+ */
+ svbool_t
+ test3 ()
+ {
+   return svtrn2_b32 (svptrue_b8 (), svptrue_b32 ());
+ }
+ 
+ /*
+ ** test4:
+ **	...
+ **	ptrue	(p[0-3])\.s, all
+ **	...
+ **	trn2	p0\.s, \1\.s, p[0-3]\.s
+ **	ret
+ */
+ svbool_t
+ test4 ()
+ {
+   return svtrn2_b32 (svptrue_b32 (), svptrue_b8 ());
+ }
+ 
+ /*
+ ** test5:
+ **	...
+ **	ptrue	(p[0-3])\.d, all
+ **	...
+ **	trn2	p0\.d, p[0-3]\.d, \1\.d
+ **	ret
+ */
+ svbool_t
+ test5 ()
+ {
+   return svtrn2_b64 (svptrue_b8 (), svptrue_b64 ());
+ }
+ 
+ /*
+ ** test6:
+ **	...
+ **	ptrue	(p[0-3])\.d, all
+ **	...
+ **	trn2	p0\.d, \1\.d, p[0-3]\.d
+ **	ret
+ */
+ svbool_t
+ test6 ()
+ {
+   return svtrn2_b64 (svptrue_b64 (), svptrue_b8 ());
+ }
+ 
+ #ifdef __cplusplus
+ }
+ #endif
diff -Nrcpad gcc-14-20250808/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_4.c gcc-14-20250815/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_4.c
*** gcc-14-20250808/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_4.c	Thu Jan  1 00:00:00 1970
--- gcc-14-20250815/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_4.c	Fri Aug 15 22:32:16 2025
***************
*** 0 ****
--- 1,96 ----
+ /* { dg-options "-O2" } */
+ /* { dg-final { check-function-bodies "**" "" } } */
+ 
+ #include <arm_sve.h>
+ 
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
+ 
+ /*
+ ** test1:
+ **	...
+ **	ptrue	(p[0-3])\.h, all
+ **	...
+ **	zip1	p0\.h, p[0-3]\.h, \1\.h
+ **	ret
+ */
+ svbool_t
+ test1 ()
+ {
+   return svzip1_b16 (svptrue_b8 (), svptrue_b16 ());
+ }
+ 
+ /*
+ ** test2:
+ **	...
+ **	ptrue	(p[0-3])\.h, all
+ **	...
+ **	zip1	p0\.h, \1\.h, p[0-3]\.h
+ **	ret
+ */
+ svbool_t
+ test2 ()
+ {
+   return svzip1_b16 (svptrue_b16 (), svptrue_b8 ());
+ }
+ 
+ /*
+ ** test3:
+ **	...
+ **	ptrue	(p[0-3])\.s, all
+ **	...
+ **	zip1	p0\.s, p[0-3]\.s, \1\.s
+ **	ret
+ */
+ svbool_t
+ test3 ()
+ {
+   return svzip1_b32 (svptrue_b8 (), svptrue_b32 ());
+ }
+ 
+ /*
+ ** test4:
+ **	...
+ **	ptrue	(p[0-3])\.s, all
+ **	...
+ **	zip1	p0\.s, \1\.s, p[0-3]\.s
+ **	ret
+ */
+ svbool_t
+ test4 ()
+ {
+   return svzip1_b32 (svptrue_b32 (), svptrue_b8 ());
+ }
+ 
+ /*
+ ** test5:
+ **	...
+ **	ptrue	(p[0-3])\.d, all
+ **	...
+ **	zip1	p0\.d, p[0-3]\.d, \1\.d
+ **	ret
+ */
+ svbool_t
+ test5 ()
+ {
+   return svzip1_b64 (svptrue_b8 (), svptrue_b64 ());
+ }
+ 
+ /*
+ ** test6:
+ **	...
+ **	ptrue	(p[0-3])\.d, all
+ **	...
+ **	zip1	p0\.d, \1\.d, p[0-3]\.d
+ **	ret
+ */
+ svbool_t
+ test6 ()
+ {
+   return svzip1_b64 (svptrue_b64 (), svptrue_b8 ());
+ }
+ 
+ #ifdef __cplusplus
+ }
+ #endif
diff -Nrcpad gcc-14-20250808/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_5.c gcc-14-20250815/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_5.c
*** gcc-14-20250808/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_5.c	Thu Jan  1 00:00:00 1970
--- gcc-14-20250815/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_5.c	Fri Aug 15 22:32:16 2025
***************
*** 0 ****
--- 1,96 ----
+ /* { dg-options "-O2" } */
+ /* { dg-final { check-function-bodies "**" "" } } */
+ 
+ #include <arm_sve.h>
+ 
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
+ 
+ /*
+ ** test1:
+ **	...
+ **	ptrue	(p[0-3])\.h, all
+ **	...
+ **	zip2	p0\.h, p[0-3]\.h, \1\.h
+ **	ret
+ */
+ svbool_t
+ test1 ()
+ {
+   return svzip2_b16 (svptrue_b8 (), svptrue_b16 ());
+ }
+ 
+ /*
+ ** test2:
+ **	...
+ **	ptrue	(p[0-3])\.h, all
+ **	...
+ **	zip2	p0\.h, \1\.h, p[0-3]\.h
+ **	ret
+ */
+ svbool_t
+ test2 ()
+ {
+   return svzip2_b16 (svptrue_b16 (), svptrue_b8 ());
+ }
+ 
+ /*
+ ** test3:
+ **	...
+ **	ptrue	(p[0-3])\.s, all
+ **	...
+ **	zip2	p0\.s, p[0-3]\.s, \1\.s
+ **	ret
+ */
+ svbool_t
+ test3 ()
+ {
+   return svzip2_b32 (svptrue_b8 (), svptrue_b32 ());
+ }
+ 
+ /*
+ ** test4:
+ **	...
+ **	ptrue	(p[0-3])\.s, all
+ **	...
+ **	zip2	p0\.s, \1\.s, p[0-3]\.s
+ **	ret
+ */
+ svbool_t
+ test4 ()
+ {
+   return svzip2_b32 (svptrue_b32 (), svptrue_b8 ());
+ }
+ 
+ /*
+ ** test5:
+ **	...
+ **	ptrue	(p[0-3])\.d, all
+ **	...
+ **	zip2	p0\.d, p[0-3]\.d, \1\.d
+ **	ret
+ */
+ svbool_t
+ test5 ()
+ {
+   return svzip2_b64 (svptrue_b8 (), svptrue_b64 ());
+ }
+ 
+ /*
+ ** test6:
+ **	...
+ **	ptrue	(p[0-3])\.d, all
+ **	...
+ **	zip2	p0\.d, \1\.d, p[0-3]\.d
+ **	ret
+ */
+ svbool_t
+ test6 ()
+ {
+   return svzip2_b64 (svptrue_b64 (), svptrue_b8 ());
+ }
+ 
+ #ifdef __cplusplus
+ }
+ #endif
diff -Nrcpad gcc-14-20250808/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_6.c gcc-14-20250815/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_6.c
*** gcc-14-20250808/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_6.c	Thu Jan  1 00:00:00 1970
--- gcc-14-20250815/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_6.c	Fri Aug 15 22:32:16 2025
***************
*** 0 ****
--- 1,96 ----
+ /* { dg-options "-O2" } */
+ /* { dg-final { check-function-bodies "**" "" } } */
+ 
+ #include <arm_sve.h>
+ 
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
+ 
+ /*
+ ** test1:
+ **	...
+ **	ptrue	(p[0-3])\.h, all
+ **	...
+ **	uzp1	p0\.h, p[0-3]\.h, \1\.h
+ **	ret
+ */
+ svbool_t
+ test1 ()
+ {
+   return svuzp1_b16 (svptrue_b8 (), svptrue_b16 ());
+ }
+ 
+ /*
+ ** test2:
+ **	...
+ **	ptrue	(p[0-3])\.h, all
+ **	...
+ **	uzp1	p0\.h, \1\.h, p[0-3]\.h
+ **	ret
+ */
+ svbool_t
+ test2 ()
+ {
+   return svuzp1_b16 (svptrue_b16 (), svptrue_b8 ());
+ }
+ 
+ /*
+ ** test3:
+ **	...
+ **	ptrue	(p[0-3])\.s, all
+ **	...
+ **	uzp1	p0\.s, p[0-3]\.s, \1\.s
+ **	ret
+ */
+ svbool_t
+ test3 ()
+ {
+   return svuzp1_b32 (svptrue_b8 (), svptrue_b32 ());
+ }
+ 
+ /*
+ ** test4:
+ **	...
+ **	ptrue	(p[0-3])\.s, all
+ **	...
+ **	uzp1	p0\.s, \1\.s, p[0-3]\.s
+ **	ret
+ */
+ svbool_t
+ test4 ()
+ {
+   return svuzp1_b32 (svptrue_b32 (), svptrue_b8 ());
+ }
+ 
+ /*
+ ** test5:
+ **	...
+ **	ptrue	(p[0-3])\.d, all
+ **	...
+ **	uzp1	p0\.d, p[0-3]\.d, \1\.d
+ **	ret
+ */
+ svbool_t
+ test5 ()
+ {
+   return svuzp1_b64 (svptrue_b8 (), svptrue_b64 ());
+ }
+ 
+ /*
+ ** test6:
+ **	...
+ **	ptrue	(p[0-3])\.d, all
+ **	...
+ **	uzp1	p0\.d, \1\.d, p[0-3]\.d
+ **	ret
+ */
+ svbool_t
+ test6 ()
+ {
+   return svuzp1_b64 (svptrue_b64 (), svptrue_b8 ());
+ }
+ 
+ #ifdef __cplusplus
+ }
+ #endif
diff -Nrcpad gcc-14-20250808/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_7.c gcc-14-20250815/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_7.c
*** gcc-14-20250808/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_7.c	Thu Jan  1 00:00:00 1970
--- gcc-14-20250815/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_7.c	Fri Aug 15 22:32:16 2025
***************
*** 0 ****
--- 1,96 ----
+ /* { dg-options "-O2" } */
+ /* { dg-final { check-function-bodies "**" "" } } */
+ 
+ #include <arm_sve.h>
+ 
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
+ 
+ /*
+ ** test1:
+ **	...
+ **	ptrue	(p[0-3])\.h, all
+ **	...
+ **	uzp2	p0\.h, p[0-3]\.h, \1\.h
+ **	ret
+ */
+ svbool_t
+ test1 ()
+ {
+   return svuzp2_b16 (svptrue_b8 (), svptrue_b16 ());
+ }
+ 
+ /*
+ ** test2:
+ **	...
+ **	ptrue	(p[0-3])\.h, all
+ **	...
+ **	uzp2	p0\.h, \1\.h, p[0-3]\.h
+ **	ret
+ */
+ svbool_t
+ test2 ()
+ {
+   return svuzp2_b16 (svptrue_b16 (), svptrue_b8 ());
+ }
+ 
+ /*
+ ** test3:
+ **	...
+ **	ptrue	(p[0-3])\.s, all
+ **	...
+ **	uzp2	p0\.s, p[0-3]\.s, \1\.s
+ **	ret
+ */
+ svbool_t
+ test3 ()
+ {
+   return svuzp2_b32 (svptrue_b8 (), svptrue_b32 ());
+ }
+ 
+ /*
+ ** test4:
+ **	...
+ **	ptrue	(p[0-3])\.s, all
+ **	...
+ **	uzp2	p0\.s, \1\.s, p[0-3]\.s
+ **	ret
+ */
+ svbool_t
+ test4 ()
+ {
+   return svuzp2_b32 (svptrue_b32 (), svptrue_b8 ());
+ }
+ 
+ /*
+ ** test5:
+ **	...
+ **	ptrue	(p[0-3])\.d, all
+ **	...
+ **	uzp2	p0\.d, p[0-3]\.d, \1\.d
+ **	ret
+ */
+ svbool_t
+ test5 ()
+ {
+   return svuzp2_b64 (svptrue_b8 (), svptrue_b64 ());
+ }
+ 
+ /*
+ ** test6:
+ **	...
+ **	ptrue	(p[0-3])\.d, all
+ **	...
+ **	uzp2	p0\.d, \1\.d, p[0-3]\.d
+ **	ret
+ */
+ svbool_t
+ test6 ()
+ {
+   return svuzp2_b64 (svptrue_b64 (), svptrue_b8 ());
+ }
+ 
+ #ifdef __cplusplus
+ }
+ #endif
diff -Nrcpad gcc-14-20250808/gcc/testsuite/gcc.target/aarch64/sve/acle/general/rev_2.c gcc-14-20250815/gcc/testsuite/gcc.target/aarch64/sve/acle/general/rev_2.c
*** gcc-14-20250808/gcc/testsuite/gcc.target/aarch64/sve/acle/general/rev_2.c	Thu Jan  1 00:00:00 1970
--- gcc-14-20250815/gcc/testsuite/gcc.target/aarch64/sve/acle/general/rev_2.c	Fri Aug 15 22:32:16 2025
***************
*** 0 ****
--- 1,27 ----
+ /* { dg-do compile } */
+ /* { dg-options "-O2" } */
+ 
+ #include <arm_sve.h>
+ 
+ svbool_t test1()
+ {
+   return svrev_b16 (svptrue_b16 ());
+ }
+ 
+ svbool_t test2()
+ {
+   return svrev_b32 (svptrue_b32 ());
+ }
+ 
+ svbool_t test3()
+ {
+   return svrev_b64 (svptrue_b64 ());
+ }
+ 
+ /* { dg-final { scan-assembler {\tptrue\tp[0-7]\.h} } } */
+ /* { dg-final { scan-assembler {\tptrue\tp[0-7]\.s} } } */
+ /* { dg-final { scan-assembler {\tptrue\tp[0-7]\.d} } } */
+ /* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.b} } } */
+ /* { dg-final { scan-assembler {\trev\tp0\.h} } } */
+ /* { dg-final { scan-assembler {\trev\tp0\.s} } } */
+ /* { dg-final { scan-assembler {\trev\tp0\.d} } } */
diff -Nrcpad gcc-14-20250808/gcc/testsuite/gcc.target/i386/pr121208-1a.c gcc-14-20250815/gcc/testsuite/gcc.target/i386/pr121208-1a.c
*** gcc-14-20250808/gcc/testsuite/gcc.target/i386/pr121208-1a.c	Thu Jan  1 00:00:00 1970
--- gcc-14-20250815/gcc/testsuite/gcc.target/i386/pr121208-1a.c	Fri Aug 15 22:32:33 2025
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile { target *-*-linux* } } */
+ /* { dg-options "-O2 -fPIC -mno-sse -mno-mmx -mno-80387 -mtls-dialect=gnu" } */
+ 
+ extern __thread int bar;
+ extern void func (void);
+ 
+ __attribute__((no_caller_saved_registers))
+ void
+ foo (int error)
+ {
+   bar = 1; /* { dg-error -mtls-dialect=gnu2 } */
+   if (error == 0)
+     func ();
+   bar = 0;
+ }
diff -Nrcpad gcc-14-20250808/gcc/testsuite/gcc.target/i386/pr121208-1b.c gcc-14-20250815/gcc/testsuite/gcc.target/i386/pr121208-1b.c
*** gcc-14-20250808/gcc/testsuite/gcc.target/i386/pr121208-1b.c	Thu Jan  1 00:00:00 1970
--- gcc-14-20250815/gcc/testsuite/gcc.target/i386/pr121208-1b.c	Fri Aug 15 22:32:33 2025
***************
*** 0 ****
--- 1,4 ----
+ /* { dg-do compile { target *-*-linux* } } */
+ /* { dg-options "-O2 -fPIC -mno-sse -mno-mmx -mno-80387 -mtls-dialect=gnu2" } */
+ 
+ #include "pr121208-1a.c"
diff -Nrcpad gcc-14-20250808/gcc/testsuite/gcc.target/i386/pr121208-2a.c gcc-14-20250815/gcc/testsuite/gcc.target/i386/pr121208-2a.c
*** gcc-14-20250808/gcc/testsuite/gcc.target/i386/pr121208-2a.c	Thu Jan  1 00:00:00 1970
--- gcc-14-20250815/gcc/testsuite/gcc.target/i386/pr121208-2a.c	Fri Aug 15 22:32:33 2025
***************
*** 0 ****
--- 1,17 ----
+ /* { dg-do compile { target *-*-linux* } } */
+ /* { dg-options "-O2 -fPIC -mtls-dialect=gnu" } */
+ 
+ typedef unsigned int uword_t __attribute__ ((mode (__word__)));
+ extern __thread int bar;
+ extern void func (void);
+ 
+ __attribute__((target("general-regs-only")))
+ __attribute__((interrupt))
+ void
+ foo (void *frame, uword_t error)
+ {
+   bar = 1; /* { dg-error -mtls-dialect=gnu2 } */
+   if (error == 0)
+     func ();
+   bar = 0;
+ }
diff -Nrcpad gcc-14-20250808/gcc/testsuite/gcc.target/i386/pr121208-2b.c gcc-14-20250815/gcc/testsuite/gcc.target/i386/pr121208-2b.c
*** gcc-14-20250808/gcc/testsuite/gcc.target/i386/pr121208-2b.c	Thu Jan  1 00:00:00 1970
--- gcc-14-20250815/gcc/testsuite/gcc.target/i386/pr121208-2b.c	Fri Aug 15 22:32:33 2025
***************
*** 0 ****
--- 1,4 ----
+ /* { dg-do compile { target *-*-linux* } } */
+ /* { dg-options "-O2 -fPIC -mtls-dialect=gnu2" } */
+ 
+ #include "pr121208-2a.c"
diff -Nrcpad gcc-14-20250808/gcc/testsuite/gcc.target/i386/pr121208-3a.c gcc-14-20250815/gcc/testsuite/gcc.target/i386/pr121208-3a.c
*** gcc-14-20250808/gcc/testsuite/gcc.target/i386/pr121208-3a.c	Thu Jan  1 00:00:00 1970
--- gcc-14-20250815/gcc/testsuite/gcc.target/i386/pr121208-3a.c	Fri Aug 15 22:32:33 2025
***************
*** 0 ****
--- 1,17 ----
+ /* { dg-do compile { target *-*-linux* } } */
+ /* { dg-options "-O2 -fPIC -mtls-dialect=gnu" } */
+ 
+ typedef unsigned int uword_t __attribute__ ((mode (__word__)));
+ extern __thread int bar;
+ extern void func (void);
+ 
+ __attribute__((target("general-regs-only")))
+ __attribute__((interrupt))
+ void
+ foo (void *frame)
+ {
+   bar = 1; /* { dg-error -mtls-dialect=gnu2 } */
+   if (frame == 0)
+     func ();
+   bar = 0;
+ }
diff -Nrcpad gcc-14-20250808/gcc/testsuite/gcc.target/i386/pr121208-3b.c gcc-14-20250815/gcc/testsuite/gcc.target/i386/pr121208-3b.c
*** gcc-14-20250808/gcc/testsuite/gcc.target/i386/pr121208-3b.c	Thu Jan  1 00:00:00 1970
--- gcc-14-20250815/gcc/testsuite/gcc.target/i386/pr121208-3b.c	Fri Aug 15 22:32:33 2025
***************
*** 0 ****
--- 1,4 ----
+ /* { dg-do compile { target *-*-linux* } } */
+ /* { dg-options "-O2 -fPIC -mtls-dialect=gnu2" } */
+ 
+ #include "pr121208-3a.c"
diff -Nrcpad gcc-14-20250808/gcc/testsuite/gcc.target/loongarch/pr121542.c gcc-14-20250815/gcc/testsuite/gcc.target/loongarch/pr121542.c
*** gcc-14-20250808/gcc/testsuite/gcc.target/loongarch/pr121542.c	Thu Jan  1 00:00:00 1970
--- gcc-14-20250815/gcc/testsuite/gcc.target/loongarch/pr121542.c	Fri Aug 15 22:32:34 2025
***************
*** 0 ****
--- 1,54 ----
+ /* { dg-do compile } */
+ /* { dg-options "-mrecip=all  -mfrecipe -mabi=lp64d -march=loongarch64 -mfpu=64 -msimd=lasx -Ofast" } */
+ 
+ typedef long unsigned int STRLEN;
+ typedef struct sv SV;
+ struct sv
+ {
+   void *sv_any;
+   unsigned int sv_refcnt;
+   unsigned int sv_flags;
+ };
+ typedef struct xpv XPV;
+ struct xpv
+ {
+   char *xpv_pv;
+   STRLEN xpv_cur;
+   STRLEN xpv_len;
+ };
+ typedef unsigned long UV;
+ extern char *PL_bufend;
+ extern char *d;
+ SV *Perl_newSV (STRLEN len);
+ 
+ char *
+ S_scan_const (char *start)
+ {
+   register char *send = PL_bufend;
+   SV *sv = Perl_newSV (send - start);
+   register char *s = start;
+   UV uv;
+ 
+   while (s < send)
+     {
+       if (!(((UV)(uv)) < 0x80))
+         {
+           int hicount = 0;
+           unsigned char *c;
+           for (c = (unsigned char *)((XPV *)(sv)->sv_any)->xpv_pv;
+                c < (unsigned char *)d; c++)
+             {
+               if (!(((UV)(*c)) < 0x80))
+                 {
+                   hicount++;
+                 }
+             }
+           d += hicount;
+           *d++ = (char)uv;
+         }
+ 
+       s++;
+     }
+ 
+   return s;
+ }
diff -Nrcpad gcc-14-20250808/gcc/testsuite/lib/multiline.exp gcc-14-20250815/gcc/testsuite/lib/multiline.exp
*** gcc-14-20250808/gcc/testsuite/lib/multiline.exp	Fri Aug  8 22:33:55 2025
--- gcc-14-20250815/gcc/testsuite/lib/multiline.exp	Fri Aug 15 22:32:42 2025
*************** proc handle-multiline-outputs { text } {
*** 153,158 ****
--- 153,161 ----
      # If dg-enable-nn-line-numbers was provided, then obscure source-margin
      # line numbers by converting them to "NN" form.
      set text [maybe-handle-nn-line-numbers $text]
+ 
+     # Remove Windows .exe suffix
+     regsub -all "(as|cc1|cc1plus|collect2|f951|ld|lto-wrapper)\.exe?:" $text {\1:} text
      
      set index 0
      foreach entry $multiline_expected_outputs {
diff -Nrcpad gcc-14-20250808/gcc/testsuite/lib/target-supports.exp gcc-14-20250815/gcc/testsuite/lib/target-supports.exp
*** gcc-14-20250808/gcc/testsuite/lib/target-supports.exp	Fri Aug  8 22:33:55 2025
--- gcc-14-20250815/gcc/testsuite/lib/target-supports.exp	Fri Aug 15 22:32:42 2025
*************** proc add_options_for_aarch64_sve { flags
*** 5388,5393 ****
--- 5388,5400 ----
      return "$flags -march=armv8.2-a+sve"
  }
  
+ proc add_options_for_aarch64_sme { flags } {
+     if { ![istarget aarch64*-*-*] || [check_effective_target_aarch64_sme] } {
+ 	return "$flags"
+     }
+     return "$flags -march=armv9-a+sme"
+ }
+ 
  # Return 1 if this is an ARM target supporting the FP16 alternative
  # format.  Some multilibs may be incompatible with the options needed.  Also
  # set et_arm_fp16_alternative_flags to the best options to add.
*************** foreach N { 128 256 512 1024 2048 } {
*** 6037,6042 ****
--- 6044,6065 ----
      }]
  }
  
+ # Return true if this is an AArch64 target that can run SME code.
+ 
+ proc check_effective_target_aarch64_sme_hw { } {
+     if { ![istarget aarch64*-*-*] } {
+ 	return 0
+     }
+     return [check_runtime aarch64_sme_hw_available {
+ 	int
+ 	main (void)
+ 	{
+ 	  asm volatile ("rdsvl x0, #1");
+ 	  return 0;
+ 	}
+     } [add_options_for_aarch64_sme ""]]
+ }
+ 
  proc check_effective_target_arm_neonv2_hw { } {
      return [check_runtime arm_neon_hwv2_available {
  	#include "arm_neon.h"
diff -Nrcpad gcc-14-20250808/libgcc/config/aarch64/linux-unwind.h gcc-14-20250815/libgcc/config/aarch64/linux-unwind.h
*** gcc-14-20250808/libgcc/config/aarch64/linux-unwind.h	Fri Aug  8 22:33:57 2025
--- gcc-14-20250815/libgcc/config/aarch64/linux-unwind.h	Fri Aug 15 22:32:44 2025
***************
*** 27,33 ****
  
  #include <signal.h>
  #include <sys/ucontext.h>
! 
  
  /* Since insns are always stored LE, on a BE system the opcodes will
     be loaded byte-reversed.  Therefore, define two sets of opcodes,
--- 27,33 ----
  
  #include <signal.h>
  #include <sys/ucontext.h>
! #include <stdint.h>
  
  /* Since insns are always stored LE, on a BE system the opcodes will
     be loaded byte-reversed.  Therefore, define two sets of opcodes,
***************
*** 43,48 ****
--- 43,64 ----
  
  #define MD_FALLBACK_FRAME_STATE_FOR aarch64_fallback_frame_state
  
+ #ifndef FPSIMD_MAGIC
+ #define FPSIMD_MAGIC 0x46508001
+ #endif
+ 
+ #ifndef TPIDR2_MAGIC
+ #define TPIDR2_MAGIC 0x54504902
+ #endif
+ 
+ #ifndef ZA_MAGIC
+ #define ZA_MAGIC 0x54366345
+ #endif
+ 
+ #ifndef EXTRA_MAGIC
+ #define EXTRA_MAGIC 0x45585401
+ #endif
+ 
  static _Unwind_Reason_Code
  aarch64_fallback_frame_state (struct _Unwind_Context *context,
  			      _Unwind_FrameState * fs)
*************** aarch64_fallback_frame_state (struct _Un
*** 58,63 ****
--- 74,94 ----
      ucontext_t uc;
    };
  
+   struct tpidr2_block
+   {
+     uint64_t za_save_buffer;
+     uint16_t num_za_save_slices;
+     uint8_t reserved[6];
+   };
+ 
+   struct za_block
+   {
+     struct _aarch64_ctx head;
+     uint16_t vl;
+     uint16_t reserved[3];
+     uint64_t data;
+   };
+ 
    struct rt_sigframe *rt_;
    _Unwind_Ptr new_cfa;
    unsigned *pc = context->ra;
*************** aarch64_fallback_frame_state (struct _Un
*** 103,113 ****
--- 134,148 ----
       field can be used to skip over unrecognized context extensions.
       The end of the context sequence is marked by a context with magic
       0 or size 0.  */
+   struct tpidr2_block *tpidr2 = 0;
+   struct za_block *za_ctx = 0;
+ 
    for (extension_marker = (struct _aarch64_ctx *) &sc->__reserved;
         extension_marker->magic;
         extension_marker = (struct _aarch64_ctx *)
         ((unsigned char *) extension_marker + extension_marker->size))
      {
+     restart:
        if (extension_marker->magic == FPSIMD_MAGIC)
  	{
  	  struct fpsimd_context *ctx =
*************** aarch64_fallback_frame_state (struct _Un
*** 139,150 ****
--- 174,256 ----
  	      fs->regs.reg[AARCH64_DWARF_V0 + i].loc.offset = offset;
  	    }
  	}
+       else if (extension_marker->magic == TPIDR2_MAGIC)
+ 	{
+ 	  /* A TPIDR2 context.
+ 
+ 	     All the casting is to support big-endian ILP32.  We could read
+ 	     directly into TPIDR2 otherwise.  */
+ 	  struct { struct _aarch64_ctx h; uint64_t tpidr2; } *ctx
+ 		  = (void *)extension_marker;
+ #if defined (__ILP32__)
+ 	  tpidr2 = (struct tpidr2_block *) (uintptr_t) ctx->tpidr2;
+ #else
+ 	  tpidr2 = (struct tpidr2_block *) ctx->tpidr2;
+ #endif
+ 	}
+       else if (extension_marker->magic == ZA_MAGIC)
+ 	/* A ZA context.  We interpret this later.  */
+ 	za_ctx = (void *)extension_marker;
+       else if (extension_marker->magic == EXTRA_MAGIC)
+ 	{
+ 	  /* Extra context.  The ABI guarantees that the next _aarch64_ctx
+ 	     in the current list will be the zero terminator, so we can simply
+ 	     switch to the new list and continue from there.  The new list is
+ 	     also zero-terminated.
+ 
+ 	     As above, the casting is to support big-endian ILP32.  */
+ 	  struct { struct _aarch64_ctx h; uint64_t next; } *ctx
+ 		  = (void *)extension_marker;
+ #if defined (__ILP32__)
+ 	  extension_marker = (struct _aarch64_ctx *) (uintptr_t) ctx->next;
+ #else
+ 	  extension_marker = (struct _aarch64_ctx *) ctx->next;
+ #endif
+ 	  goto restart;
+ 	}
        else
  	{
  	  /* There is context provided that we do not recognize!  */
  	}
      }
  
+   /* Signal handlers are entered with ZA in the off state (TPIDR2_ELO==0 and
+      PSTATE.ZA==0).  The normal process when transitioning from ZA being
+      dormant to ZA being off is to commit the lazy save; see the AAPCS64
+      for details.  However, this is not done when entering a signal handler.
+      Instead, linux saves the old contents of ZA and TPIDR2_EL0 to the
+      sigcontext without interpreting them further.
+ 
+      Therefore, if a signal handler throws an exception to code outside the
+      signal handler, the unwinder must commit the lazy save after the fact.
+      Committing a lazy save means:
+ 
+      (1) Storing the contents of ZA into the buffer provided by TPIDR2_EL0.
+      (2) Setting TPIDR2_EL0 to zero.
+      (3) Turning ZA off.
+ 
+      (2) and (3) have already been done by the call to __libgcc_arm_za_disable.
+      (1) involves copying data from the ZA sigcontext entry to the
+      corresponding lazy save buffer.  */
+   if (tpidr2 && za_ctx && tpidr2->za_save_buffer)
+     {
+       /* There is a 16-bit vector length (measured in bytes) at ZA_CTX + 8.
+ 	 The data itself starts at ZA_CTX + 16.
+ 	 As above, the casting is to support big-endian ILP32.  */
+       uint16_t vl = za_ctx->vl;
+ #if defined (__ILP32__)
+       void *save_buffer = (void *) (uintptr_t) tpidr2->za_save_buffer;
+       const void *za_buffer = (void *) (uintptr_t) &za_ctx->data;
+ #else
+       void *save_buffer = (void *) tpidr2->za_save_buffer;
+       const void *za_buffer = (void *) &za_ctx->data;
+ #endif
+       uint64_t num_slices = tpidr2->num_za_save_slices;
+       if (num_slices > vl)
+ 	num_slices = vl;
+       memcpy (save_buffer, za_buffer, num_slices * vl);
+     }
+ 
    fs->regs.how[31] = REG_SAVED_OFFSET;
    fs->regs.reg[31].loc.offset = (_Unwind_Ptr) & (sc->sp) - new_cfa;
  
