diff -Nrcpad gcc-14-20250912/LAST_UPDATED gcc-14-20250919/LAST_UPDATED
*** gcc-14-20250912/LAST_UPDATED	Fri Sep 12 22:32:49 2025
--- gcc-14-20250919/LAST_UPDATED	Fri Sep 19 22:33:24 2025
***************
*** 1 ****
! Obtained from git: releases/gcc-14 revision a2d57a88ec90ca61ddff0e41c4d63b14ea874850
--- 1 ----
! Obtained from git: releases/gcc-14 revision 0f44647a337275fc3cc96c07afd1eb20b5b1651b
diff -Nrcpad gcc-14-20250912/MD5SUMS gcc-14-20250919/MD5SUMS
*** gcc-14-20250912/MD5SUMS	Fri Sep 12 22:32:58 2025
--- gcc-14-20250919/MD5SUMS	Fri Sep 19 22:33:29 2025
***************
*** 1,5 ****
  # This file contains the MD5 checksums of the files in the
! # gcc-14-20250912.tar.xz tarball.
  #
  # Besides verifying that all files in the tarball were correctly expanded,
  # it also can be used to determine if any files have changed since the
--- 1,5 ----
  # This file contains the MD5 checksums of the files in the
! # gcc-14-20250919.tar.xz tarball.
  #
  # Besides verifying that all files in the tarball were correctly expanded,
  # it also can be used to determine if any files have changed since the
*************** fc9280b02bc68e4fb1ef8d51ccc25061  Change
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*** 4190,4196 ****
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*************** e2e50c477f234875fd9fc66727097083  gcc/co
*** 5096,5102 ****
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*************** d36a2aabdf8da39363d9be0efef739b0  gcc/co
*** 5361,5367 ****
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*************** d3c17c84efdf6a50d26f287b397fc85f  gcc/cp
*** 5434,5440 ****
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--- 5434,5440 ----
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*************** aa1c9493107eefcfd7a64479fccc57e8  gcc/di
*** 5753,5759 ****
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--- 5753,5759 ----
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*** 6429,6435 ****
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--- 6429,6435 ----
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*************** e8a9eb01b9451a357155e7152df1c669  gcc/ta
*** 8060,8066 ****
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*** 14019,14024 ****
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*************** bb692e50ab2bed2943d200f6f0097d3a  gcc/te
*** 58621,58626 ****
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*************** e95ad2780e346935674e8e065a322d1d  gcc/te
*** 65074,65083 ****
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  f7e509420aab463592a3e5d54b6c6b8c  gcc/testsuite/gcc.target/arm/fp16-builtins-1.c
  237aa223257ca24bfddebcc43dd387a2  gcc/testsuite/gcc.target/arm/fp16-compile-alt-1.c
  85be9f1d24d495b2882fc58bb89a96d2  gcc/testsuite/gcc.target/arm/fp16-compile-alt-10.c
--- 65076,65082 ----
  80ad1d4eaf61d16f656cb80332dc22f4  gcc/testsuite/gcc.target/arm/fma.h
  220c0d4f4cad22e6687747e0fe55f267  gcc/testsuite/gcc.target/arm/fmaxmin.c
  a1182e17a398d2114e6f9d6156618a24  gcc/testsuite/gcc.target/arm/fmaxmin.x
! d8203dd017181ab133e278b2250a10d4  gcc/testsuite/gcc.target/arm/fp16-aapcs.c
  f7e509420aab463592a3e5d54b6c6b8c  gcc/testsuite/gcc.target/arm/fp16-builtins-1.c
  237aa223257ca24bfddebcc43dd387a2  gcc/testsuite/gcc.target/arm/fp16-compile-alt-1.c
  85be9f1d24d495b2882fc58bb89a96d2  gcc/testsuite/gcc.target/arm/fp16-compile-alt-10.c
*************** cbaafd43310e10a7ba4ce687bafe06da  gcc/te
*** 74521,74531 ****
  89d909d7d758041e829631ac800bf196  gcc/testsuite/gcc.target/i386/pieces-memcpy-15.c
  437a6c001b5f504cb8a978424f9f229c  gcc/testsuite/gcc.target/i386/pieces-memcpy-16.c
  a0fc0b89838032f850b17823a354b986  gcc/testsuite/gcc.target/i386/pieces-memcpy-17.c
! ce99ca62859e3b5ee0e5695b59309237  gcc/testsuite/gcc.target/i386/pieces-memcpy-18.c
  b5f6fb3aaac27e15ae52d9111e60d98d  gcc/testsuite/gcc.target/i386/pieces-memcpy-19.c
  279c04d20615905ca5bf2f44eb5a231d  gcc/testsuite/gcc.target/i386/pieces-memcpy-2.c
  7e2d486487e1f536c226d8bc290fd8ad  gcc/testsuite/gcc.target/i386/pieces-memcpy-20.c
! 2f4b551b9d6addea576cff08a8831f3f  gcc/testsuite/gcc.target/i386/pieces-memcpy-21.c
  483ed3c0a5b3efe685343cb5dc87d54d  gcc/testsuite/gcc.target/i386/pieces-memcpy-22.c
  2820c9b91ec98c38843764eea07d4b75  gcc/testsuite/gcc.target/i386/pieces-memcpy-3.c
  698986063dd5ba005476ca849de14359  gcc/testsuite/gcc.target/i386/pieces-memcpy-4.c
--- 74520,74530 ----
  89d909d7d758041e829631ac800bf196  gcc/testsuite/gcc.target/i386/pieces-memcpy-15.c
  437a6c001b5f504cb8a978424f9f229c  gcc/testsuite/gcc.target/i386/pieces-memcpy-16.c
  a0fc0b89838032f850b17823a354b986  gcc/testsuite/gcc.target/i386/pieces-memcpy-17.c
! 7a34703054f1d16fc3e3de2cc1b87012  gcc/testsuite/gcc.target/i386/pieces-memcpy-18.c
  b5f6fb3aaac27e15ae52d9111e60d98d  gcc/testsuite/gcc.target/i386/pieces-memcpy-19.c
  279c04d20615905ca5bf2f44eb5a231d  gcc/testsuite/gcc.target/i386/pieces-memcpy-2.c
  7e2d486487e1f536c226d8bc290fd8ad  gcc/testsuite/gcc.target/i386/pieces-memcpy-20.c
! 9d90237b50551a44a67d354724502ebb  gcc/testsuite/gcc.target/i386/pieces-memcpy-21.c
  483ed3c0a5b3efe685343cb5dc87d54d  gcc/testsuite/gcc.target/i386/pieces-memcpy-22.c
  2820c9b91ec98c38843764eea07d4b75  gcc/testsuite/gcc.target/i386/pieces-memcpy-3.c
  698986063dd5ba005476ca849de14359  gcc/testsuite/gcc.target/i386/pieces-memcpy-4.c
*************** ab6fa2bfe98c867fab182d157d457706  gcc/te
*** 74574,74583 ****
  d98f40e3e5aa8e8b9f5499569f688965  gcc/testsuite/gcc.target/i386/pieces-memset-43.c
  2b47b7f82aeabc7a238642520819b3f0  gcc/testsuite/gcc.target/i386/pieces-memset-44.c
  86947bff2a1eb3faba119670600994db  gcc/testsuite/gcc.target/i386/pieces-memset-45.c
! f29f6d2af05e1f08f148f0eed162d860  gcc/testsuite/gcc.target/i386/pieces-memset-46.c
  8f0614f1d8cbc09d9e6e515b9c85586c  gcc/testsuite/gcc.target/i386/pieces-memset-47.c
  fab4224ceed336ed6902793909c0c6c2  gcc/testsuite/gcc.target/i386/pieces-memset-48.c
! b6a5763cac2b72e43f0900c7fbca0740  gcc/testsuite/gcc.target/i386/pieces-memset-49.c
  e59e962761850423b307c01f720c8e84  gcc/testsuite/gcc.target/i386/pieces-memset-5.c
  f6afe5571570af54d1d2e02c0e28d3f6  gcc/testsuite/gcc.target/i386/pieces-memset-50.c
  587ca57e48d1c64f4cb91b6203512c99  gcc/testsuite/gcc.target/i386/pieces-memset-51.c
--- 74573,74582 ----
  d98f40e3e5aa8e8b9f5499569f688965  gcc/testsuite/gcc.target/i386/pieces-memset-43.c
  2b47b7f82aeabc7a238642520819b3f0  gcc/testsuite/gcc.target/i386/pieces-memset-44.c
  86947bff2a1eb3faba119670600994db  gcc/testsuite/gcc.target/i386/pieces-memset-45.c
! 3647374ee718421444609e296cfa0ad2  gcc/testsuite/gcc.target/i386/pieces-memset-46.c
  8f0614f1d8cbc09d9e6e515b9c85586c  gcc/testsuite/gcc.target/i386/pieces-memset-47.c
  fab4224ceed336ed6902793909c0c6c2  gcc/testsuite/gcc.target/i386/pieces-memset-48.c
! 9f2ed79a200ad2a71bf00d1e582aae79  gcc/testsuite/gcc.target/i386/pieces-memset-49.c
  e59e962761850423b307c01f720c8e84  gcc/testsuite/gcc.target/i386/pieces-memset-5.c
  f6afe5571570af54d1d2e02c0e28d3f6  gcc/testsuite/gcc.target/i386/pieces-memset-50.c
  587ca57e48d1c64f4cb91b6203512c99  gcc/testsuite/gcc.target/i386/pieces-memset-51.c
*************** dd0d54001d5c0c89de9ecbfeca7d9163  gcc/te
*** 87430,87435 ****
--- 87429,87437 ----
  18a30b21905501cfe3b583c13b3c756a  gcc/testsuite/gcc.target/s390/vector/vec-clobber-1.c
  f4f003702feb568dbc88ed411b2783e9  gcc/testsuite/gcc.target/s390/vector/vec-cmp-1.c
  6ad5106106095fa0defa7e045850f1a6  gcc/testsuite/gcc.target/s390/vector/vec-cmp-2.c
+ 43da7697d65673c784c720bf722bedd0  gcc/testsuite/gcc.target/s390/vector/vec-cmp-emu-1.c
+ ae9432c5505fa00769af44de635efdd0  gcc/testsuite/gcc.target/s390/vector/vec-cmp-emu-2.c
+ 84259de43489373910ab6e819d3c5f9d  gcc/testsuite/gcc.target/s390/vector/vec-cmp-emu-3.c
  3dea3f0d6272507210edfbf3ebbcbaee  gcc/testsuite/gcc.target/s390/vector/vec-cmpge.c
  836ebd984394712bf83085d3675ab39b  gcc/testsuite/gcc.target/s390/vector/vec-copysign-execute.c
  b2d0a0fe9bc2bcd1f0cf523b66f2c66f  gcc/testsuite/gcc.target/s390/vector/vec-copysign.c
*************** d828e38384c506bf5e7d5a3c02725a37  libssp
*** 123676,123682 ****
  7bb3c32ba0a48d1cf785305e1b783eb6  libssp/strncpy-chk.c
  a19c79c1d86436e86b0fee41e6cf6b15  libssp/vsnprintf-chk.c
  145156e880b03115b393070d0ed37be3  libssp/vsprintf-chk.c
! 379b298030a79c77a8487ffe12f3483c  libstdc++-v3/ChangeLog
  7aa6c40440a44fcf5ec94c066160c2f8  libstdc++-v3/ChangeLog-1998
  7aff86600b6a1ed3fa87305075a92db0  libstdc++-v3/ChangeLog-1999
  a6f28e8fc9bb07696a9e068b439a3a87  libstdc++-v3/ChangeLog-2000
--- 123678,123684 ----
  7bb3c32ba0a48d1cf785305e1b783eb6  libssp/strncpy-chk.c
  a19c79c1d86436e86b0fee41e6cf6b15  libssp/vsnprintf-chk.c
  145156e880b03115b393070d0ed37be3  libssp/vsprintf-chk.c
! db3d5c2ab8b7fe800aa517fa9e3b7116  libstdc++-v3/ChangeLog
  7aa6c40440a44fcf5ec94c066160c2f8  libstdc++-v3/ChangeLog-1998
  7aff86600b6a1ed3fa87305075a92db0  libstdc++-v3/ChangeLog-1999
  a6f28e8fc9bb07696a9e068b439a3a87  libstdc++-v3/ChangeLog-2000
*************** e44faa2816a5abc669c4063837761dc4  libstd
*** 124494,124500 ****
  599296af3dc0d5011fd39fb803fbccd2  libstdc++-v3/include/bits/unicode.h
  2a07c5fd938c277d16917fa79db295da  libstdc++-v3/include/bits/uniform_int_dist.h
  4c0ff2b76d8499d565fe166dc5782d62  libstdc++-v3/include/bits/unique_lock.h
! bf0cf7215202e6f8b50bf2bc32902f37  libstdc++-v3/include/bits/unique_ptr.h
  b9acb3112a876e3d1b56d44802b27c56  libstdc++-v3/include/bits/unordered_map.h
  ae02656017359d0b5f1cb3253d2058bb  libstdc++-v3/include/bits/unordered_set.h
  c4eaa17487280545ea73bc9386afcd4b  libstdc++-v3/include/bits/uses_allocator.h
--- 124496,124502 ----
  599296af3dc0d5011fd39fb803fbccd2  libstdc++-v3/include/bits/unicode.h
  2a07c5fd938c277d16917fa79db295da  libstdc++-v3/include/bits/uniform_int_dist.h
  4c0ff2b76d8499d565fe166dc5782d62  libstdc++-v3/include/bits/unique_lock.h
! 519fb186198f4055e56d3f86a3c1dee9  libstdc++-v3/include/bits/unique_ptr.h
  b9acb3112a876e3d1b56d44802b27c56  libstdc++-v3/include/bits/unordered_map.h
  ae02656017359d0b5f1cb3253d2058bb  libstdc++-v3/include/bits/unordered_set.h
  c4eaa17487280545ea73bc9386afcd4b  libstdc++-v3/include/bits/uses_allocator.h
*************** f9819c3fbab884d0ff4d0150023c3826  libstd
*** 125043,125049 ****
  132bbb9d90975f7f11e2ba4b77bc3bbf  libstdc++-v3/include/pstl/numeric_impl.h
  531b6552c2b0ded549ed9bc9b03bebf4  libstdc++-v3/include/pstl/parallel_backend.h
  c6ea5607259b8e63bb887db39136b942  libstdc++-v3/include/pstl/parallel_backend_serial.h
! f440b4cc9ed25dc734c39310ac196140  libstdc++-v3/include/pstl/parallel_backend_tbb.h
  e128e525f970f3948feec2f4750919a8  libstdc++-v3/include/pstl/parallel_backend_utils.h
  688f2289e52048ec70461174eadd2efe  libstdc++-v3/include/pstl/parallel_impl.h
  fc443edc98096342d5fc5be5a9455d4b  libstdc++-v3/include/pstl/pstl_config.h
--- 125045,125051 ----
  132bbb9d90975f7f11e2ba4b77bc3bbf  libstdc++-v3/include/pstl/numeric_impl.h
  531b6552c2b0ded549ed9bc9b03bebf4  libstdc++-v3/include/pstl/parallel_backend.h
  c6ea5607259b8e63bb887db39136b942  libstdc++-v3/include/pstl/parallel_backend_serial.h
! 2d644ccc23c0dc8e402d7080e69ef350  libstdc++-v3/include/pstl/parallel_backend_tbb.h
  e128e525f970f3948feec2f4750919a8  libstdc++-v3/include/pstl/parallel_backend_utils.h
  688f2289e52048ec70461174eadd2efe  libstdc++-v3/include/pstl/parallel_impl.h
  fc443edc98096342d5fc5be5a9455d4b  libstdc++-v3/include/pstl/pstl_config.h
diff -Nrcpad gcc-14-20250912/gcc/ChangeLog gcc-14-20250919/gcc/ChangeLog
*** gcc-14-20250912/gcc/ChangeLog	Fri Sep 12 22:32:06 2025
--- gcc-14-20250919/gcc/ChangeLog	Fri Sep 19 22:32:19 2025
***************
*** 1,3 ****
--- 1,63 ----
+ 2025-09-18  hongtao.liu  <hongtao.liu@intel.com>
+ 
+ 	Backported from master:
+ 	2025-09-18  hongtao.liu  <hongtao.liu@intel.com>
+ 
+ 	* config/i386/x86-tune.def (X86_TUNE_AVX512_MOVE_BY_PIECES):
+ 	Remove SPR/GNR/DMR.
+ 	(X86_TUNE_AVX512_STORE_BY_PIECES): Ditto.
+ 
+ 2025-09-16  Jeff Law  <jlaw@ventanamicro.com>
+ 
+ 	Backported from master:
+ 	2025-09-12  Jeff Law  <jlaw@ventanamicro.com>
+ 
+ 	* lra-constraints.cc (get_equiv): Bounds check before accessing
+ 	data in ira_reg_equiv.
+ 
+ 2025-09-15  Kyrylo Tkachov  <ktkachov@nvidia.com>
+ 
+ 	Backported from master:
+ 	2025-09-03  Kyrylo Tkachov  <ktkachov@nvidia.com>
+ 
+ 	PR target/121749
+ 	* config/aarch64/aarch64-simd.md (aarch64_<shrn_op>shrn_n<mode>):
+ 	Use aarch64_simd_shift_imm_offset_<vn_mode> instead of
+ 	aarch64_simd_shift_imm_offset_<ve_mode> predicate.
+ 	(aarch64_<shrn_op>shrn_n<mode> VQN define_expand): Likewise.
+ 	(*aarch64_<shrn_op>rshrn_n<mode>_insn): Likewise.
+ 	(aarch64_<shrn_op>rshrn_n<mode>): Likewise.
+ 	(aarch64_<shrn_op>rshrn_n<mode> VQN define_expand): Likewise.
+ 	(aarch64_sqshrun_n<mode>_insn): Likewise.
+ 	(aarch64_sqshrun_n<mode>): Likewise.
+ 	(aarch64_sqshrun_n<mode> VQN define_expand): Likewise.
+ 	(aarch64_sqrshrun_n<mode>_insn): Likewise.
+ 	(aarch64_sqrshrun_n<mode>): Likewise.
+ 	(aarch64_sqrshrun_n<mode>): Likewise.
+ 	* config/aarch64/iterators.md (vn_mode): Handle DI, SI, HI modes.
+ 
+ 2025-09-15  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	Backported from master:
+ 	2025-09-15  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	* config/avr/avr-mcus.def: Add avr32eb14, avr32eb20,
+ 	avr32eb28, avr32eb32.
+ 	* doc/avr-mmcu.texi: Rebuild.
+ 
+ 2025-09-15  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>
+ 
+ 	Backported from master:
+ 	2024-07-16  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>
+ 
+ 	* config/s390/vector.md (V_HW): Enable V1TI unconditionally and
+ 	add TI.
+ 	(vec_cmpu<VIT_HW:mode><VIT_HW:mode>): Add 128-bit integer
+ 	variants.
+ 	(*vec_cmpeq<mode><mode>_nocc_emu): Emulate operation.
+ 	(*vec_cmpgt<mode><mode>_nocc_emu): Emulate operation.
+ 	(*vec_cmpgtu<mode><mode>_nocc_emu): Emulate operation.
+ 
  2025-09-10  Georg-Johann Lay  <avr@gjlay.de>
  
  	Backported from master:
diff -Nrcpad gcc-14-20250912/gcc/DATESTAMP gcc-14-20250919/gcc/DATESTAMP
*** gcc-14-20250912/gcc/DATESTAMP	Fri Sep 12 22:32:06 2025
--- gcc-14-20250919/gcc/DATESTAMP	Fri Sep 19 22:32:19 2025
***************
*** 1 ****
! 20250912
--- 1 ----
! 20250919
diff -Nrcpad gcc-14-20250912/gcc/config/aarch64/aarch64-simd.md gcc-14-20250919/gcc/config/aarch64/aarch64-simd.md
*** gcc-14-20250912/gcc/config/aarch64/aarch64-simd.md	Fri Sep 12 22:32:07 2025
--- gcc-14-20250919/gcc/config/aarch64/aarch64-simd.md	Fri Sep 19 22:32:27 2025
***************
*** 6514,6520 ****
  	(SAT_TRUNC:<VNARROWQ>
  	  (<TRUNC_SHIFT>:SD_HSDI
  	    (match_operand:SD_HSDI 1 "register_operand" "w")
! 	    (match_operand:SI 2 "aarch64_simd_shift_imm_offset_<ve_mode>"))))]
    "TARGET_SIMD"
    "<shrn_op>shrn\t%<vn2>0<Vmntype>, %<v>1<Vmtype>, %2"
    [(set_attr "type" "neon_shift_imm_narrow_q")]
--- 6514,6520 ----
  	(SAT_TRUNC:<VNARROWQ>
  	  (<TRUNC_SHIFT>:SD_HSDI
  	    (match_operand:SD_HSDI 1 "register_operand" "w")
! 	    (match_operand:SI 2 "aarch64_simd_shift_imm_offset_<vn_mode>"))))]
    "TARGET_SIMD"
    "<shrn_op>shrn\t%<vn2>0<Vmntype>, %<v>1<Vmtype>, %2"
    [(set_attr "type" "neon_shift_imm_narrow_q")]
***************
*** 6536,6542 ****
  	(ALL_TRUNC:<VNARROWQ>
  	  (<TRUNC_SHIFT>:VQN
  	    (match_operand:VQN 1 "register_operand")
! 	    (match_operand:SI 2 "aarch64_simd_shift_imm_offset_<ve_mode>"))))]
    "TARGET_SIMD"
    {
      operands[2] = aarch64_simd_gen_const_vector_dup (<MODE>mode,
--- 6536,6542 ----
  	(ALL_TRUNC:<VNARROWQ>
  	  (<TRUNC_SHIFT>:VQN
  	    (match_operand:VQN 1 "register_operand")
! 	    (match_operand:SI 2 "aarch64_simd_shift_imm_offset_<vn_mode>"))))]
    "TARGET_SIMD"
    {
      operands[2] = aarch64_simd_gen_const_vector_dup (<MODE>mode,
***************
*** 6567,6573 ****
  	      (<TRUNCEXTEND>:<DWI>
  	        (match_operand:SD_HSDI 1 "register_operand" "w"))
  	      (match_operand:<DWI> 3 "aarch64_int_rnd_operand"))
! 	    (match_operand:SI 2 "aarch64_simd_shift_imm_offset_<ve_mode>"))))]
    "TARGET_SIMD
     && aarch64_const_vec_rnd_cst_p (operands[3], operands[2])"
    "<shrn_op>rshrn\t%<vn2>0<Vmntype>, %<v>1<Vmtype>, %2"
--- 6567,6573 ----
  	      (<TRUNCEXTEND>:<DWI>
  	        (match_operand:SD_HSDI 1 "register_operand" "w"))
  	      (match_operand:<DWI> 3 "aarch64_int_rnd_operand"))
! 	    (match_operand:SI 2 "aarch64_simd_shift_imm_offset_<vn_mode>"))))]
    "TARGET_SIMD
     && aarch64_const_vec_rnd_cst_p (operands[3], operands[2])"
    "<shrn_op>rshrn\t%<vn2>0<Vmntype>, %<v>1<Vmtype>, %2"
***************
*** 6582,6588 ****
  	      (<TRUNCEXTEND>:<V2XWIDE>
  	        (match_operand:SD_HSDI 1 "register_operand"))
  	      (match_dup 3))
! 	    (match_operand:SI 2 "aarch64_simd_shift_imm_offset_<ve_mode>"))))]
    "TARGET_SIMD"
    {
      /* Use this expander to create the rounding constant vector, which is
--- 6582,6588 ----
  	      (<TRUNCEXTEND>:<V2XWIDE>
  	        (match_operand:SD_HSDI 1 "register_operand"))
  	      (match_dup 3))
! 	    (match_operand:SI 2 "aarch64_simd_shift_imm_offset_<vn_mode>"))))]
    "TARGET_SIMD"
    {
      /* Use this expander to create the rounding constant vector, which is
***************
*** 6602,6608 ****
  	      (<TRUNCEXTEND>:<V2XWIDE>
  	        (match_operand:VQN 1 "register_operand"))
  	      (match_dup 3))
! 	    (match_operand:SI 2 "aarch64_simd_shift_imm_offset_<ve_mode>"))))]
    "TARGET_SIMD"
    {
      if (<CODE> == TRUNCATE
--- 6602,6608 ----
  	      (<TRUNCEXTEND>:<V2XWIDE>
  	        (match_operand:VQN 1 "register_operand"))
  	      (match_dup 3))
! 	    (match_operand:SI 2 "aarch64_simd_shift_imm_offset_<vn_mode>"))))]
    "TARGET_SIMD"
    {
      if (<CODE> == TRUNCATE
***************
*** 6644,6650 ****
  	  (smax:SD_HSDI
  	    (ashiftrt:SD_HSDI
  	      (match_operand:SD_HSDI 1 "register_operand" "w")
! 	      (match_operand:SI 2 "aarch64_simd_shift_imm_offset_<ve_mode>"))
  	    (const_int 0))
  	  (const_int <half_mask>)))]
    "TARGET_SIMD"
--- 6644,6650 ----
  	  (smax:SD_HSDI
  	    (ashiftrt:SD_HSDI
  	      (match_operand:SD_HSDI 1 "register_operand" "w")
! 	      (match_operand:SI 2 "aarch64_simd_shift_imm_offset_<vn_mode>"))
  	    (const_int 0))
  	  (const_int <half_mask>)))]
    "TARGET_SIMD"
***************
*** 6655,6661 ****
  (define_expand "aarch64_sqshrun_n<mode>"
    [(match_operand:<VNARROWQ> 0 "register_operand")
     (match_operand:SD_HSDI 1 "register_operand")
!    (match_operand:SI 2 "aarch64_simd_shift_imm_offset_<ve_mode>")]
    "TARGET_SIMD"
    {
      rtx dst = gen_reg_rtx (<MODE>mode);
--- 6655,6661 ----
  (define_expand "aarch64_sqshrun_n<mode>"
    [(match_operand:<VNARROWQ> 0 "register_operand")
     (match_operand:SD_HSDI 1 "register_operand")
!    (match_operand:SI 2 "aarch64_simd_shift_imm_offset_<vn_mode>")]
    "TARGET_SIMD"
    {
      rtx dst = gen_reg_rtx (<MODE>mode);
***************
*** 6673,6679 ****
  	    (smax:VQN
  	      (ashiftrt:VQN
  		(match_operand:VQN 1 "register_operand")
! 		(match_operand:SI 2 "aarch64_simd_shift_imm_offset_<ve_mode>"))
  	      (match_dup 3))
  	    (match_dup 4))))]
    "TARGET_SIMD"
--- 6673,6679 ----
  	    (smax:VQN
  	      (ashiftrt:VQN
  		(match_operand:VQN 1 "register_operand")
! 		(match_operand:SI 2 "aarch64_simd_shift_imm_offset_<vn_mode>"))
  	      (match_dup 3))
  	    (match_dup 4))))]
    "TARGET_SIMD"
***************
*** 6715,6721 ****
  		(sign_extend:<DWI>
  		  (match_operand:SD_HSDI 1 "register_operand" "w"))
  		(match_operand:<DWI> 3 "aarch64_int_rnd_operand"))
! 	      (match_operand:SI 2 "aarch64_simd_shift_imm_offset_<ve_mode>"))
  	    (const_int 0))
  	  (const_int <half_mask>)))]
    "TARGET_SIMD
--- 6715,6721 ----
  		(sign_extend:<DWI>
  		  (match_operand:SD_HSDI 1 "register_operand" "w"))
  		(match_operand:<DWI> 3 "aarch64_int_rnd_operand"))
! 	      (match_operand:SI 2 "aarch64_simd_shift_imm_offset_<vn_mode>"))
  	    (const_int 0))
  	  (const_int <half_mask>)))]
    "TARGET_SIMD
***************
*** 6727,6733 ****
  (define_expand "aarch64_sqrshrun_n<mode>"
    [(match_operand:<VNARROWQ> 0 "register_operand")
     (match_operand:SD_HSDI 1 "register_operand")
!    (match_operand:SI 2 "aarch64_simd_shift_imm_offset_<ve_mode>")]
    "TARGET_SIMD"
    {
      int prec = GET_MODE_UNIT_PRECISION (<DWI>mode);
--- 6727,6733 ----
  (define_expand "aarch64_sqrshrun_n<mode>"
    [(match_operand:<VNARROWQ> 0 "register_operand")
     (match_operand:SD_HSDI 1 "register_operand")
!    (match_operand:SI 2 "aarch64_simd_shift_imm_offset_<vn_mode>")]
    "TARGET_SIMD"
    {
      int prec = GET_MODE_UNIT_PRECISION (<DWI>mode);
***************
*** 6750,6756 ****
  		  (sign_extend:<V2XWIDE>
  		    (match_operand:VQN 1 "register_operand"))
  		  (match_dup 3))
! 		(match_operand:SI 2 "aarch64_simd_shift_imm_offset_<ve_mode>"))
  	      (match_dup 4))
  	    (match_dup 5))))]
    "TARGET_SIMD"
--- 6750,6756 ----
  		  (sign_extend:<V2XWIDE>
  		    (match_operand:VQN 1 "register_operand"))
  		  (match_dup 3))
! 		(match_operand:SI 2 "aarch64_simd_shift_imm_offset_<vn_mode>"))
  	      (match_dup 4))
  	    (match_dup 5))))]
    "TARGET_SIMD"
diff -Nrcpad gcc-14-20250912/gcc/config/aarch64/iterators.md gcc-14-20250919/gcc/config/aarch64/iterators.md
*** gcc-14-20250912/gcc/config/aarch64/iterators.md	Fri Sep 12 22:32:07 2025
--- gcc-14-20250919/gcc/config/aarch64/iterators.md	Fri Sep 19 22:32:27 2025
***************
*** 1941,1947 ****
  			   (SI   "si")])
  
  ;; Like ve_mode but for the half-width modes.
! (define_mode_attr vn_mode [(V8HI  "qi") (V4SI  "hi") (V2DI  "si")])
  
  ;; Vm for lane instructions is restricted to FP_LO_REGS.
  (define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x")
--- 1941,1948 ----
  			   (SI   "si")])
  
  ;; Like ve_mode but for the half-width modes.
! (define_mode_attr vn_mode [(V8HI  "qi") (V4SI  "hi") (V2DI  "si") (DI "si")
! 			   (SI "hi") (HI "qi")])
  
  ;; Vm for lane instructions is restricted to FP_LO_REGS.
  (define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x")
diff -Nrcpad gcc-14-20250912/gcc/config/avr/avr-mcus.def gcc-14-20250919/gcc/config/avr/avr-mcus.def
*** gcc-14-20250912/gcc/config/avr/avr-mcus.def	Fri Sep 12 22:32:07 2025
--- gcc-14-20250919/gcc/config/avr/avr-mcus.def	Fri Sep 19 22:32:27 2025
*************** AVR_MCU ("avr16eb14",        ARCH_AVRXME
*** 411,416 ****
--- 411,420 ----
  AVR_MCU ("avr16eb20",        ARCH_AVRXMEGA3, AVR_ISA_NONE,  "__AVR_AVR16EB20__",   0x7800, 0x0, 0x4000, 0x8000)
  AVR_MCU ("avr16eb28",        ARCH_AVRXMEGA3, AVR_ISA_NONE,  "__AVR_AVR16EB28__",   0x7800, 0x0, 0x4000, 0x8000)
  AVR_MCU ("avr16eb32",        ARCH_AVRXMEGA3, AVR_ISA_NONE,  "__AVR_AVR16EB32__",   0x7800, 0x0, 0x4000, 0x8000)
+ AVR_MCU ("avr32eb14",        ARCH_AVRXMEGA3, AVR_ISA_NONE,  "__AVR_AVR32EB14__",   0x7400, 0x0, 0x8000, 0x8000)
+ AVR_MCU ("avr32eb20",        ARCH_AVRXMEGA3, AVR_ISA_NONE,  "__AVR_AVR32EB20__",   0x7400, 0x0, 0x8000, 0x8000)
+ AVR_MCU ("avr32eb28",        ARCH_AVRXMEGA3, AVR_ISA_NONE,  "__AVR_AVR32EB28__",   0x7400, 0x0, 0x8000, 0x8000)
+ AVR_MCU ("avr32eb32",        ARCH_AVRXMEGA3, AVR_ISA_NONE,  "__AVR_AVR32EB32__",   0x7400, 0x0, 0x8000, 0x8000)
  AVR_MCU ("avr16ea28",        ARCH_AVRXMEGA3, AVR_ISA_NONE,  "__AVR_AVR16EA28__",   0x7800, 0x0, 0x4000, 0x8000)
  AVR_MCU ("avr16ea32",        ARCH_AVRXMEGA3, AVR_ISA_NONE,  "__AVR_AVR16EA32__",   0x7800, 0x0, 0x4000, 0x8000)
  AVR_MCU ("avr16ea48",        ARCH_AVRXMEGA3, AVR_ISA_NONE,  "__AVR_AVR16EA48__",   0x7800, 0x0, 0x4000, 0x8000)
diff -Nrcpad gcc-14-20250912/gcc/config/i386/x86-tune.def gcc-14-20250919/gcc/config/i386/x86-tune.def
*** gcc-14-20250912/gcc/config/i386/x86-tune.def	Fri Sep 12 22:32:07 2025
--- gcc-14-20250919/gcc/config/i386/x86-tune.def	Fri Sep 19 22:32:28 2025
*************** DEF_TUNE (X86_TUNE_AVX256_AVOID_VEC_PERM
*** 583,588 ****
--- 583,590 ----
  /* X86_TUNE_AVX256_SPLIT_REGS: if true, AVX512 ops are split into two AVX256 ops.  */
  DEF_TUNE (X86_TUNE_AVX512_SPLIT_REGS, "avx512_split_regs", m_ZNVER4)
  
+ /* It's better to align MOVE_MAX with prefer_vector_width to reduce
+    risk of STLF stalls(small store followed by big load.)  */
  /* X86_TUNE_AVX256_MOVE_BY_PIECES: Optimize move_by_pieces with 256-bit
     AVX instructions.  */
  DEF_TUNE (X86_TUNE_AVX256_MOVE_BY_PIECES, "avx256_move_by_pieces",
*************** DEF_TUNE (X86_TUNE_AVX256_STORE_BY_PIECE
*** 596,609 ****
  /* X86_TUNE_AVX512_MOVE_BY_PIECES: Optimize move_by_pieces with 512-bit
     AVX instructions.  */
  DEF_TUNE (X86_TUNE_AVX512_MOVE_BY_PIECES, "avx512_move_by_pieces",
! 	  m_SAPPHIRERAPIDS | m_GRANITERAPIDS | m_GRANITERAPIDS_D
! 	  | m_ZNVER4 | m_ZNVER5)
  
  /* X86_TUNE_AVX512_STORE_BY_PIECES: Optimize store_by_pieces with 512-bit
     AVX instructions.  */
  DEF_TUNE (X86_TUNE_AVX512_STORE_BY_PIECES, "avx512_store_by_pieces",
! 	  m_SAPPHIRERAPIDS | m_GRANITERAPIDS | m_GRANITERAPIDS_D
! 	  | m_ZNVER4 | m_ZNVER5)
  
  /*****************************************************************************/
  /*****************************************************************************/
--- 598,609 ----
  /* X86_TUNE_AVX512_MOVE_BY_PIECES: Optimize move_by_pieces with 512-bit
     AVX instructions.  */
  DEF_TUNE (X86_TUNE_AVX512_MOVE_BY_PIECES, "avx512_move_by_pieces",
! 	   m_ZNVER4 | m_ZNVER5)
  
  /* X86_TUNE_AVX512_STORE_BY_PIECES: Optimize store_by_pieces with 512-bit
     AVX instructions.  */
  DEF_TUNE (X86_TUNE_AVX512_STORE_BY_PIECES, "avx512_store_by_pieces",
! 	  m_ZNVER4 | m_ZNVER5)
  
  /*****************************************************************************/
  /*****************************************************************************/
diff -Nrcpad gcc-14-20250912/gcc/config/s390/vector.md gcc-14-20250919/gcc/config/s390/vector.md
*** gcc-14-20250912/gcc/config/s390/vector.md	Fri Sep 12 22:32:07 2025
--- gcc-14-20250919/gcc/config/s390/vector.md	Fri Sep 19 22:32:28 2025
***************
*** 30,36 ****
  ; V_HW2 is for having two iterators expanding independently e.g. vcond.
  ; It's similar to V_HW, but not fully identical: V1TI is not included, because
  ; there are no 128-bit compares.
! (define_mode_iterator V_HW  [V16QI V8HI V4SI V2DI (V1TI "TARGET_VXE") V2DF
  			     (V4SF "TARGET_VXE") (V1TF "TARGET_VXE")
  			     (TF "TARGET_VXE")])
  (define_mode_iterator V_HW2 [V16QI V8HI V4SI V2DI V2DF (V4SF "TARGET_VXE")
--- 30,36 ----
  ; V_HW2 is for having two iterators expanding independently e.g. vcond.
  ; It's similar to V_HW, but not fully identical: V1TI is not included, because
  ; there are no 128-bit compares.
! (define_mode_iterator V_HW  [V16QI V8HI V4SI V2DI V1TI TI V2DF
  			     (V4SF "TARGET_VXE") (V1TF "TARGET_VXE")
  			     (TF "TARGET_VXE")])
  (define_mode_iterator V_HW2 [V16QI V8HI V4SI V2DI V2DF (V4SF "TARGET_VXE")
***************
*** 50,55 ****
--- 50,56 ----
  (define_mode_iterator VI_HW_HSDT [V8HI V4SI V2DI V1TI TI])
  (define_mode_iterator VI_HW_HS  [V8HI  V4SI])
  (define_mode_iterator VI_HW_QH  [V16QI V8HI])
+ (define_mode_iterator VI_HW_T   [V1TI TI])
  
  ; Directly supported vector modes with a certain number of elements
  (define_mode_iterator V_HW_2   [V2DI V2DF])
***************
*** 149,155 ****
  			    (V1HI "V1HI") (V2HI "V2HI") (V4HI "V4HI") (V8HI "V8HI")
  			    (V1SI "V1SI") (V2SI "V2SI") (V4SI "V4SI")
  			    (V1DI "V1DI") (V2DI "V2DI")
! 			    (V1TI "V1TI")
  			    (V1SF "V1SI") (V2SF "V2SI") (V4SF "V4SI")
  			    (V1DF "V1DI") (V2DF "V2DI")
  			    (V1TF "V1TI") (TF "V1TI")])
--- 150,156 ----
  			    (V1HI "V1HI") (V2HI "V2HI") (V4HI "V4HI") (V8HI "V8HI")
  			    (V1SI "V1SI") (V2SI "V2SI") (V4SI "V4SI")
  			    (V1DI "V1DI") (V2DI "V2DI")
! 			    (V1TI "V1TI") (TI "V1TI")
  			    (V1SF "V1SI") (V2SF "V2SI") (V4SF "V4SI")
  			    (V1DF "V1DI") (V2DF "V2DI")
  			    (V1TF "V1TI") (TF "V1TI")])
***************
*** 158,164 ****
  			    (V1HI "v1hi") (V2HI "v2hi") (V4HI "v4hi") (V8HI "v8hi")
  			    (V1SI "v1si") (V2SI "v2si") (V4SI "v4si")
  			    (V1DI "v1di") (V2DI "v2di")
! 			    (V1TI "v1ti")
  			    (V1SF "v1si") (V2SF "v2si") (V4SF "v4si")
  			    (V1DF "v1di") (V2DF "v2di")
  			    (V1TF "v1ti") (TF   "v1ti")])
--- 159,165 ----
  			    (V1HI "v1hi") (V2HI "v2hi") (V4HI "v4hi") (V8HI "v8hi")
  			    (V1SI "v1si") (V2SI "v2si") (V4SI "v4si")
  			    (V1DI "v1di") (V2DI "v2di")
! 			    (V1TI "v1ti") (TI "v1ti")
  			    (V1SF "v1si") (V2SF "v2si") (V4SF "v4si")
  			    (V1DF "v1di") (V2DF "v2di")
  			    (V1TF "v1ti") (TF   "v1ti")])
***************
*** 1945,1955 ****
    DONE;
  })
  
! (define_expand "vec_cmpu<VI_HW:mode><VI_HW:mode>"
!   [(set (match_operand:VI_HW    0 "register_operand" "")
! 	(match_operator:VI_HW   1 ""
! 	  [(match_operand:VI_HW 2 "register_operand" "")
! 	   (match_operand:VI_HW 3 "register_operand" "")]))]
    "TARGET_VX"
  {
    s390_expand_vec_compare (operands[0], GET_CODE(operands[1]), operands[2], operands[3]);
--- 1946,1956 ----
    DONE;
  })
  
! (define_expand "vec_cmpu<VIT_HW:mode><VIT_HW:mode>"
!   [(set (match_operand:VIT_HW    0 "register_operand" "")
! 	(match_operator:VIT_HW   1 ""
! 	  [(match_operand:VIT_HW 2 "register_operand" "")
! 	   (match_operand:VIT_HW 3 "register_operand" "")]))]
    "TARGET_VX"
  {
    s390_expand_vec_compare (operands[0], GET_CODE(operands[1]), operands[2], operands[3]);
***************
*** 1964,1969 ****
--- 1965,2058 ----
    "vc<VICMP_HW_OP:insn_cmp_op><VI:bhfgq>\t%v2,%v0,%v1"
    [(set_attr "op_type" "VRR")])
  
+ (define_insn_and_split "*vec_cmpeq<mode><mode>_nocc_emu"
+   [(set (match_operand:VI_HW_T             0 "register_operand" "=v")
+ 	(eq:VI_HW_T (match_operand:VI_HW_T 1 "register_operand"  "v")
+ 		    (match_operand:VI_HW_T 2 "register_operand"  "v")))]
+   "TARGET_VX"
+   "#"
+   "&& can_create_pseudo_p ()"
+   [(set (match_dup 3)
+ 	(eq:V2DI (match_dup 1) (match_dup 2)))
+    (set (match_dup 4)
+ 	(vec_select:V2DI (match_dup 3) (parallel [(const_int 1) (const_int 0)])))
+    (set (match_dup 3)
+ 	(and:V2DI (match_dup 3) (match_dup 4)))
+    (set (match_dup 0)
+ 	(subreg:<MODE> (match_dup 3) 0))]
+ {
+   operands[1] = simplify_gen_subreg (V2DImode, operands[1], <MODE>mode, 0);
+   operands[2] = simplify_gen_subreg (V2DImode, operands[2], <MODE>mode, 0);
+   operands[3] = gen_reg_rtx (V2DImode);
+   operands[4] = gen_reg_rtx (V2DImode);
+ })
+ 
+ (define_insn_and_split "*vec_cmpgt<mode><mode>_nocc_emu"
+   [(set (match_operand:VI_HW_T             0 "register_operand" "=v")
+ 	(gt:VI_HW_T (match_operand:VI_HW_T 1 "register_operand"  "v")
+ 		    (match_operand:VI_HW_T 2 "register_operand"  "v")))]
+   "TARGET_VX"
+   "#"
+   "&& can_create_pseudo_p ()"
+   [(set (match_dup 3)
+ 	(gt:V2DI (match_dup 1) (match_dup 2)))
+    (set (match_dup 4)
+ 	(eq:V2DI (match_dup 1) (match_dup 2)))
+    (set (match_dup 5)
+ 	(gtu:V2DI (match_dup 1) (match_dup 2)))
+    (set (match_dup 5)
+ 	(vec_select:V2DI (match_dup 5) (parallel [(const_int 1) (const_int 0)])))
+    (set (match_dup 4)
+ 	(and:V2DI (match_dup 4) (match_dup 5)))
+    (set (match_dup 4)
+ 	(ior:V2DI (match_dup 3) (match_dup 4)))
+    (set (match_dup 4)
+ 	(vec_duplicate:V2DI
+ 	 (vec_select:DI
+ 	  (match_dup 4)
+ 	  (parallel [(const_int 1)]))))
+    (set (match_dup 0)
+ 	(subreg:<MODE> (match_dup 4) 0))]
+ {
+   operands[1] = simplify_gen_subreg (V2DImode, operands[1], <MODE>mode, 0);
+   operands[2] = simplify_gen_subreg (V2DImode, operands[2], <MODE>mode, 0);
+   operands[3] = gen_reg_rtx (V2DImode);
+   operands[4] = gen_reg_rtx (V2DImode);
+   operands[5] = gen_reg_rtx (V2DImode);
+ })
+ 
+ (define_insn_and_split "*vec_cmpgtu<mode><mode>_nocc_emu"
+   [(set (match_operand:VI_HW_T              0 "register_operand" "=v")
+ 	(gtu:VI_HW_T (match_operand:VI_HW_T 1 "register_operand"  "v")
+ 		     (match_operand:VI_HW_T 2 "register_operand"  "v")))]
+   "TARGET_VX"
+   "#"
+   "&& can_create_pseudo_p ()"
+   [(set (match_dup 3)
+ 	(gtu:V2DI (match_dup 1) (match_dup 2)))
+    (set (match_dup 4)
+ 	(eq:V2DI (match_dup 1) (match_dup 2)))
+    (set (match_dup 5)
+ 	(vec_select:V2DI (match_dup 3) (parallel [(const_int 1) (const_int 0)])))
+    (set (match_dup 4)
+ 	(and:V2DI (match_dup 4) (match_dup 5)))
+    (set (match_dup 4)
+ 	(ior:V2DI (match_dup 3) (match_dup 4)))
+    (set (match_dup 4)
+ 	(vec_duplicate:V2DI
+ 	 (vec_select:DI
+ 	  (match_dup 4)
+ 	  (parallel [(const_int 1)]))))
+    (set (match_dup 0)
+ 	(subreg:<MODE> (match_dup 4) 0))]
+ {
+   operands[1] = simplify_gen_subreg (V2DImode, operands[1], <MODE>mode, 0);
+   operands[2] = simplify_gen_subreg (V2DImode, operands[2], <MODE>mode, 0);
+   operands[3] = gen_reg_rtx (V2DImode);
+   operands[4] = gen_reg_rtx (V2DImode);
+   operands[5] = gen_reg_rtx (V2DImode);
+ })
+ 
  
  ;;
  ;; Floating point compares
***************
*** 2300,2311 ****
  
  ; op0 = op3 == 0 ? op1 : op2
  (define_insn "*vec_sel0<mode>"
!   [(set (match_operand:V 0 "register_operand" "=v")
! 	(if_then_else:V
  	 (eq (match_operand:<TOINTVEC> 3 "register_operand" "v")
  	     (match_operand:<TOINTVEC> 4 "const0_operand" ""))
! 	 (match_operand:V 1 "register_operand" "v")
! 	 (match_operand:V 2 "register_operand" "v")))]
    "TARGET_VX"
    "vsel\t%v0,%2,%1,%3"
    [(set_attr "op_type" "VRR")])
--- 2389,2400 ----
  
  ; op0 = op3 == 0 ? op1 : op2
  (define_insn "*vec_sel0<mode>"
!   [(set (match_operand:VT 0 "register_operand" "=v")
! 	(if_then_else:VT
  	 (eq (match_operand:<TOINTVEC> 3 "register_operand" "v")
  	     (match_operand:<TOINTVEC> 4 "const0_operand" ""))
! 	 (match_operand:VT 1 "register_operand" "v")
! 	 (match_operand:VT 2 "register_operand" "v")))]
    "TARGET_VX"
    "vsel\t%v0,%2,%1,%3"
    [(set_attr "op_type" "VRR")])
diff -Nrcpad gcc-14-20250912/gcc/cp/ChangeLog gcc-14-20250919/gcc/cp/ChangeLog
*** gcc-14-20250912/gcc/cp/ChangeLog	Fri Sep 12 22:32:07 2025
--- gcc-14-20250919/gcc/cp/ChangeLog	Fri Sep 19 22:32:28 2025
***************
*** 1,3 ****
--- 1,12 ----
+ 2025-09-15  Matthias Kretz  <m.kretz@gsi.de>
+ 
+ 	Backported from master:
+ 	2025-09-09  Matthias Kretz  <m.kretz@gsi.de>
+ 
+ 	PR c++/121801
+ 	* mangle.cc (write_real_cst): Handle 16-bit real and assert
+ 	that reals have 16 bits or a multiple of 32 bits.
+ 
  2025-08-08  Patrick Palka  <ppalka@redhat.com>
  
  	Backported from master:
diff -Nrcpad gcc-14-20250912/gcc/cp/mangle.cc gcc-14-20250919/gcc/cp/mangle.cc
*** gcc-14-20250912/gcc/cp/mangle.cc	Fri Sep 12 22:32:07 2025
--- gcc-14-20250919/gcc/cp/mangle.cc	Fri Sep 19 22:32:28 2025
*************** write_real_cst (const tree value)
*** 2160,2170 ****
    int i, limit, dir;
  
    tree type = TREE_TYPE (value);
!   int words = GET_MODE_BITSIZE (SCALAR_FLOAT_TYPE_MODE (type)) / 32;
  
    real_to_target (target_real, &TREE_REAL_CST (value),
  		  TYPE_MODE (type));
  
    /* The value in target_real is in the target word order,
       so we must write it out backward if that happens to be
       little-endian.  write_number cannot be used, it will
--- 2160,2183 ----
    int i, limit, dir;
  
    tree type = TREE_TYPE (value);
!   int bits = GET_MODE_BITSIZE (SCALAR_FLOAT_TYPE_MODE (type));
!   int words = bits / 32;
  
    real_to_target (target_real, &TREE_REAL_CST (value),
  		  TYPE_MODE (type));
  
+   if (words == 0)
+     {
+       /* _Float16 and std::bfloat16_t are the only supported types smaller than
+ 	 32 bits.  */
+       gcc_assert (bits == 16);
+       sprintf (buffer, "%04lx", (unsigned long) target_real[0]);
+       write_chars (buffer, 4);
+       return;
+     }
+ 
+   gcc_assert (bits % 32 == 0);
+ 
    /* The value in target_real is in the target word order,
       so we must write it out backward if that happens to be
       little-endian.  write_number cannot be used, it will
diff -Nrcpad gcc-14-20250912/gcc/doc/avr-mmcu.texi gcc-14-20250919/gcc/doc/avr-mmcu.texi
*** gcc-14-20250912/gcc/doc/avr-mmcu.texi	Fri Sep 12 22:32:07 2025
--- gcc-14-20250919/gcc/doc/avr-mmcu.texi	Fri Sep 19 22:32:28 2025
***************
*** 54,60 ****
  
  @item @anchor{avrxmega3}avrxmega3
  ``XMEGA'' devices with up to 64@tie{}KiB of combined program memory and RAM, and with program memory visible in the RAM address space.
! @*@var{mcu}@tie{}= @code{attiny202}, @code{attiny204}, @code{attiny212}, @code{attiny214}, @code{attiny402}, @code{attiny404}, @code{attiny406}, @code{attiny412}, @code{attiny414}, @code{attiny416}, @code{attiny416auto}, @code{attiny417}, @code{attiny424}, @code{attiny426}, @code{attiny427}, @code{attiny804}, @code{attiny806}, @code{attiny807}, @code{attiny814}, @code{attiny816}, @code{attiny817}, @code{attiny824}, @code{attiny826}, @code{attiny827}, @code{attiny1604}, @code{attiny1606}, @code{attiny1607}, @code{attiny1614}, @code{attiny1616}, @code{attiny1617}, @code{attiny1624}, @code{attiny1626}, @code{attiny1627}, @code{attiny3214}, @code{attiny3216}, @code{attiny3217}, @code{attiny3224}, @code{attiny3226}, @code{attiny3227}, @code{atmega808}, @code{atmega809}, @code{atmega1608}, @code{atmega1609}, @code{atmega3208}, @code{atmega3209}, @code{atmega4808}, @code{atmega4809}, @code{avr16dd14}, @code{avr16dd20}, @code{avr16dd28}, @code{avr16dd32}, @code{avr16du14}, @code{avr16du20}, @code{avr16du28}, @code{avr16du32}, @code{avr16ea28}, @code{avr16ea32}, @code{avr16ea48}, @code{avr16eb14}, @code{avr16eb20}, @code{avr16eb28}, @code{avr16eb32}, @code{avr32da28}, @code{avr32da28s}, @code{avr32da32}, @code{avr32da32s}, @code{avr32da48}, @code{avr32da48s}, @code{avr32db28}, @code{avr32db32}, @code{avr32db48}, @code{avr32dd14}, @code{avr32dd20}, @code{avr32dd28}, @code{avr32dd32}, @code{avr32du14}, @code{avr32du20}, @code{avr32du28}, @code{avr32du32}, @code{avr32ea28}, @code{avr32ea32}, @code{avr32ea48}, @code{avr32sd20}, @code{avr32sd28}, @code{avr32sd32}.
  
  @item @anchor{avrxmega4}avrxmega4
  ``XMEGA'' devices with more than 64@tie{}KiB and up to 128@tie{}KiB of program memory.
--- 54,60 ----
  
  @item @anchor{avrxmega3}avrxmega3
  ``XMEGA'' devices with up to 64@tie{}KiB of combined program memory and RAM, and with program memory visible in the RAM address space.
! @*@var{mcu}@tie{}= @code{attiny202}, @code{attiny204}, @code{attiny212}, @code{attiny214}, @code{attiny402}, @code{attiny404}, @code{attiny406}, @code{attiny412}, @code{attiny414}, @code{attiny416}, @code{attiny416auto}, @code{attiny417}, @code{attiny424}, @code{attiny426}, @code{attiny427}, @code{attiny804}, @code{attiny806}, @code{attiny807}, @code{attiny814}, @code{attiny816}, @code{attiny817}, @code{attiny824}, @code{attiny826}, @code{attiny827}, @code{attiny1604}, @code{attiny1606}, @code{attiny1607}, @code{attiny1614}, @code{attiny1616}, @code{attiny1617}, @code{attiny1624}, @code{attiny1626}, @code{attiny1627}, @code{attiny3214}, @code{attiny3216}, @code{attiny3217}, @code{attiny3224}, @code{attiny3226}, @code{attiny3227}, @code{atmega808}, @code{atmega809}, @code{atmega1608}, @code{atmega1609}, @code{atmega3208}, @code{atmega3209}, @code{atmega4808}, @code{atmega4809}, @code{avr16dd14}, @code{avr16dd20}, @code{avr16dd28}, @code{avr16dd32}, @code{avr16du14}, @code{avr16du20}, @code{avr16du28}, @code{avr16du32}, @code{avr16ea28}, @code{avr16ea32}, @code{avr16ea48}, @code{avr16eb14}, @code{avr16eb20}, @code{avr16eb28}, @code{avr16eb32}, @code{avr32da28}, @code{avr32da28s}, @code{avr32da32}, @code{avr32da32s}, @code{avr32da48}, @code{avr32da48s}, @code{avr32db28}, @code{avr32db32}, @code{avr32db48}, @code{avr32dd14}, @code{avr32dd20}, @code{avr32dd28}, @code{avr32dd32}, @code{avr32du14}, @code{avr32du20}, @code{avr32du28}, @code{avr32du32}, @code{avr32ea28}, @code{avr32ea32}, @code{avr32ea48}, @code{avr32eb14}, @code{avr32eb20}, @code{avr32eb28}, @code{avr32eb32}, @code{avr32sd20}, @code{avr32sd28}, @code{avr32sd32}.
  
  @item @anchor{avrxmega4}avrxmega4
  ``XMEGA'' devices with more than 64@tie{}KiB and up to 128@tie{}KiB of program memory.
diff -Nrcpad gcc-14-20250912/gcc/lra-constraints.cc gcc-14-20250919/gcc/lra-constraints.cc
*** gcc-14-20250912/gcc/lra-constraints.cc	Fri Sep 12 22:32:08 2025
--- gcc-14-20250919/gcc/lra-constraints.cc	Fri Sep 19 22:32:28 2025
*************** get_equiv (rtx x)
*** 538,543 ****
--- 538,544 ----
    rtx res;
  
    if (! REG_P (x) || (regno = REGNO (x)) < FIRST_PSEUDO_REGISTER
+       || regno >= ira_reg_equiv_len
        || ! ira_reg_equiv[regno].defined_p
        || ! ira_reg_equiv[regno].profitable_p
        || lra_get_regno_hard_regno (regno) >= 0)
diff -Nrcpad gcc-14-20250912/gcc/testsuite/ChangeLog gcc-14-20250919/gcc/testsuite/ChangeLog
*** gcc-14-20250912/gcc/testsuite/ChangeLog	Fri Sep 12 22:32:08 2025
--- gcc-14-20250919/gcc/testsuite/ChangeLog	Fri Sep 19 22:32:29 2025
***************
*** 1,3 ****
--- 1,58 ----
+ 2025-09-18  hongtao.liu  <hongtao.liu@intel.com>
+ 
+ 	Backported from master:
+ 	2025-09-18  hongtao.liu  <hongtao.liu@intel.com>
+ 
+ 	* gcc.target/i386/pieces-memcpy-18.c: Use -mtune=znver5
+ 	instead of -mtune=sapphirerapids.
+ 	* gcc.target/i386/pieces-memcpy-21.c: Ditto.
+ 	* gcc.target/i386/pieces-memset-46.c: Ditto.
+ 	* gcc.target/i386/pieces-memset-49.c: Ditto.
+ 
+ 2025-09-17  Torbjörn SVENSSON  <torbjorn.svensson@foss.st.com>
+ 
+ 	Backported from master:
+ 	2025-09-17  Torbjörn SVENSSON  <torbjorn.svensson@foss.st.com>
+ 
+ 	* gcc.target/arm/fp16-aapcs.c: New test.
+ 	* gcc.target/arm/fp16-aapcs-1.c: Removed.
+ 	* gcc.target/arm/fp16-aapcs-2.c: Likewise.
+ 	* gcc.target/arm/fp16-aapcs-3.c: Likewise.
+ 	* gcc.target/arm/fp16-aapcs-4.c: Likewise.
+ 
+ 2025-09-15  Kyrylo Tkachov  <ktkachov@nvidia.com>
+ 
+ 	Backported from master:
+ 	2025-09-03  Kyrylo Tkachov  <ktkachov@nvidia.com>
+ 
+ 	PR target/121749
+ 	* gcc.target/aarch64/simd/pr121749.c: Use dg-assemble directive.
+ 
+ 2025-09-15  Kyrylo Tkachov  <ktkachov@nvidia.com>
+ 
+ 	Backported from master:
+ 	2025-09-03  Kyrylo Tkachov  <ktkachov@nvidia.com>
+ 
+ 	PR target/121749
+ 	* gcc.target/aarch64/simd/pr121749.c: New test.
+ 
+ 2025-09-15  Matthias Kretz  <m.kretz@gsi.de>
+ 
+ 	Backported from master:
+ 	2025-09-09  Matthias Kretz  <m.kretz@gsi.de>
+ 
+ 	PR c++/121801
+ 	* g++.dg/abi/pr121801.C: New test.
+ 
+ 2025-09-15  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>
+ 
+ 	Backported from master:
+ 	2024-07-16  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>
+ 
+ 	* gcc.target/s390/vector/vec-cmp-emu-1.c: New test.
+ 	* gcc.target/s390/vector/vec-cmp-emu-2.c: New test.
+ 	* gcc.target/s390/vector/vec-cmp-emu-3.c: New test.
+ 
  2025-08-30  liuhongt  <hongtao.liu@intel.com>
  
  	Revert:
diff -Nrcpad gcc-14-20250912/gcc/testsuite/g++.dg/abi/pr121801.C gcc-14-20250919/gcc/testsuite/g++.dg/abi/pr121801.C
*** gcc-14-20250912/gcc/testsuite/g++.dg/abi/pr121801.C	Thu Jan  1 00:00:00 1970
--- gcc-14-20250919/gcc/testsuite/g++.dg/abi/pr121801.C	Fri Sep 19 22:32:30 2025
***************
*** 0 ****
--- 1,13 ----
+ // PR c++/121801
+ // { dg-do compile { target { c++20 && float16 } } }
+ // { dg-add-options float16 }
+ 
+ template<_Float16 T> void f() {}
+ 
+ void uses() {
+   f<_Float16(1)>();
+   f<_Float16(2)>();
+ }
+ 
+ // { dg-final { scan-assembler "_Z1fILDF16_3c00EEvv" } }
+ // { dg-final { scan-assembler "_Z1fILDF16_4000EEvv" } }
diff -Nrcpad gcc-14-20250912/gcc/testsuite/gcc.target/aarch64/simd/pr121749.c gcc-14-20250919/gcc/testsuite/gcc.target/aarch64/simd/pr121749.c
*** gcc-14-20250912/gcc/testsuite/gcc.target/aarch64/simd/pr121749.c	Thu Jan  1 00:00:00 1970
--- gcc-14-20250919/gcc/testsuite/gcc.target/aarch64/simd/pr121749.c	Fri Sep 19 22:32:46 2025
***************
*** 0 ****
--- 1,11 ----
+ /* { dg-do assemble } */
+ /* { dg-options "-O2" } */
+ 
+ #include <arm_neon.h>
+ 
+ uint32_t
+ foo (uint64_t v0)
+ {
+   return vqshrnd_n_u64 (vshrd_n_u64 (v0, 26), 7);
+ }
+ 
diff -Nrcpad gcc-14-20250912/gcc/testsuite/gcc.target/arm/fp16-aapcs-1.c gcc-14-20250919/gcc/testsuite/gcc.target/arm/fp16-aapcs-1.c
*** gcc-14-20250912/gcc/testsuite/gcc.target/arm/fp16-aapcs-1.c	Fri Sep 12 22:32:16 2025
--- gcc-14-20250919/gcc/testsuite/gcc.target/arm/fp16-aapcs-1.c	Thu Jan  1 00:00:00 1970
***************
*** 1,65 ****
- /* { dg-do compile }  */
- /* { dg-require-effective-target arm_hard_vfp_ok }  */
- /* { dg-require-effective-target arm_fp16_ok } */
- /* { dg-options "-O2" }  */
- /* { dg-add-options arm_fp16_ieee } */
- /* { dg-final { check-function-bodies "**" "" "" } } */
- 
- /* Test __fp16 arguments and return value in registers (hard-float).  */
- 
- void
- swap (__fp16, __fp16);
- 
- /*
- ** F:
- ** ...
- ** (
- 
- Below block is for non-armv8.1
- ** (
- **	vmov\.f32	(s[3-9]|s1[0-5]), s0
- ** ...
- **	vmov\.f32	s0, s1
- ** ...
- **	vmov\.f32	s1, \1
- ** |
- **	vmov\.f32	(s[3-9]|s1[0-5]), s1
- ** ...
- **	vmov\.f32	s1, s0
- ** ...
- **	vmov\.f32	s0, \2
- ** )
- **	vstr\.32	s2, \[sp, #4\]	@ int
- **	bl	swap
- **	vldr\.32	s2, \[sp, #4\]	@ int
- **	vmov\.f32	s0, s2
- 
- ** |
- 
- Below block is for armv8.1
- ** (
- **	vmov	(s[3-9]|s1[0-5]), s0	@ __fp16
- ** ...
- **	vmov	s0, s1	@ __fp16
- ** ...
- **	vmov	s1, \3	@ __fp16
- ** |
- **	vmov	(s[3-9]|s1[0-5]), s1	@ __fp16
- ** ...
- **	vmov	s1, s0	@ __fp16
- ** ...
- **	vmov	s0, \4	@ __fp16
- ** )
- **	vstr\.32	s2, \[sp, #4\]	@ int
- **	bl	swap
- **	vldr\.16	s0, \[sp, #4\]
- 
- ** )
- ** ...
- */
- __fp16
- F (__fp16 a, __fp16 b, __fp16 c)
- {
-   swap (b, a);
-   return c;
- }
--- 0 ----
diff -Nrcpad gcc-14-20250912/gcc/testsuite/gcc.target/arm/fp16-aapcs-2.c gcc-14-20250919/gcc/testsuite/gcc.target/arm/fp16-aapcs-2.c
*** gcc-14-20250912/gcc/testsuite/gcc.target/arm/fp16-aapcs-2.c	Fri Sep 12 22:32:16 2025
--- gcc-14-20250919/gcc/testsuite/gcc.target/arm/fp16-aapcs-2.c	Thu Jan  1 00:00:00 1970
***************
*** 1,44 ****
- /* { dg-do compile }  */
- /* { dg-require-effective-target arm_fp16_ok } */
- /* { dg-options "-mfloat-abi=softfp -O2 -mno-long-calls" }  */
- /* { dg-add-options arm_fp16_ieee } */
- /* { dg-skip-if "incompatible float-abi" { arm*-*-* } { "-mfloat-abi=hard" } } */
- /* { dg-final { check-function-bodies "**" "" "" } } */
- 
- /* Test __fp16 arguments and return value in registers (softfp).  */
- 
- void
- swap (__fp16, __fp16);
- 
- /*
- ** F:
- ** ...
- ** (
- **	mov	r3, r0	@ __fp16
- ** ...
- **	mov	r0, r1	@ __fp16
- ** ...
- **	mov	r1, r3	@ __fp16
- ** |
- **	mov	r3, r1	@ __fp16
- ** ...
- **	mov	r1, r0	@ __fp16
- ** ...
- **	mov	r0, r3	@ __fp16
- ** )
- ** ...
- */
- /*
- ** F: { target arm_little_endian }
- ** ...
- **	str	r2, \[sp, #4\]
- **	bl	swap
- **	ldrh	r0, \[sp, #4\]	@ __fp16
- ** ...
- */
- __fp16
- F (__fp16 a, __fp16 b, __fp16 c)
- {
-   swap (b, a);
-   return c;
- }
--- 0 ----
diff -Nrcpad gcc-14-20250912/gcc/testsuite/gcc.target/arm/fp16-aapcs-3.c gcc-14-20250919/gcc/testsuite/gcc.target/arm/fp16-aapcs-3.c
*** gcc-14-20250912/gcc/testsuite/gcc.target/arm/fp16-aapcs-3.c	Fri Sep 12 22:32:16 2025
--- gcc-14-20250919/gcc/testsuite/gcc.target/arm/fp16-aapcs-3.c	Thu Jan  1 00:00:00 1970
***************
*** 1,65 ****
- /* { dg-do compile }  */
- /* { dg-require-effective-target arm_hard_vfp_ok }  */
- /* { dg-require-effective-target arm_fp16_alternative_ok } */
- /* { dg-options "-O2" }  */
- /* { dg-add-options arm_fp16_alternative } */
- /* { dg-final { check-function-bodies "**" "" "" } } */
- 
- /* Test __fp16 arguments and return value in registers (hard-float).  */
- 
- void
- swap (__fp16, __fp16);
- 
- /*
- ** F:
- ** ...
- ** (
- 
- Below block is for non-armv8.1
- ** (
- **	vmov\.f32	(s[3-9]|s1[0-5]), s0
- ** ...
- **	vmov\.f32	s0, s1
- ** ...
- **	vmov\.f32	s1, \1
- ** |
- **	vmov\.f32	(s[3-9]|s1[0-5]), s1
- ** ...
- **	vmov\.f32	s1, s0
- ** ...
- **	vmov\.f32	s0, \2
- ** )
- **	vstr\.32	s2, \[sp, #4\]	@ int
- **	bl	swap
- **	vldr\.32	s2, \[sp, #4\]	@ int
- **	vmov\.f32	s0, s2
- 
- ** |
- 
- Below block is for armv8.1
- ** (
- **	vmov	(s[3-9]|s1[0-5]), s0
- ** ...
- **	vmov	s0, s1
- ** ...
- **	vmov	s1, \3
- ** |
- **	vmov	(s[3-9]|s1[0-5]), s1
- ** ...
- **	vmov	s1, s0
- ** ...
- **	vmov	s0, \4
- ** )
- **	vstr\.32	s2, \[sp, #4\]	@ int
- **	bl	swap
- **	vldr\.16	s0, \[sp, #4\]
- 
- ** )
- ** ...
- */
- __fp16
- F (__fp16 a, __fp16 b, __fp16 c)
- {
-   swap (b, a);
-   return c;
- }
--- 0 ----
diff -Nrcpad gcc-14-20250912/gcc/testsuite/gcc.target/arm/fp16-aapcs-4.c gcc-14-20250919/gcc/testsuite/gcc.target/arm/fp16-aapcs-4.c
*** gcc-14-20250912/gcc/testsuite/gcc.target/arm/fp16-aapcs-4.c	Fri Sep 12 22:32:16 2025
--- gcc-14-20250919/gcc/testsuite/gcc.target/arm/fp16-aapcs-4.c	Thu Jan  1 00:00:00 1970
***************
*** 1,44 ****
- /* { dg-do compile }  */
- /* { dg-require-effective-target arm_fp16_alternative_ok } */
- /* { dg-options "-mfloat-abi=softfp -O2" }  */
- /* { dg-add-options arm_fp16_alternative } */
- /* { dg-skip-if "incompatible float-abi" { arm*-*-* } { "-mfloat-abi=hard" } } */
- /* { dg-final { check-function-bodies "**" "" "" } } */
- 
- /* Test __fp16 arguments and return value in registers (softfp).  */
- 
- void
- swap (__fp16, __fp16);
- 
- /*
- ** F:
- ** ...
- ** (
- **	mov	r3, r0	@ __fp16
- ** ...
- **	mov	r0, r1	@ __fp16
- ** ...
- **	mov	r1, r3	@ __fp16
- ** |
- **	mov	r3, r1	@ __fp16
- ** ...
- **	mov	r1, r0	@ __fp16
- ** ...
- **	mov	r0, r3	@ __fp16
- ** )
- ** ...
- */
- /*
- ** F: { target arm_little_endian }
- ** ...
- **	str	r2, \[sp, #4\]
- **	bl	swap
- **	ldrh	r0, \[sp, #4\]	@ __fp16
- ** ...
- */
- __fp16
- F (__fp16 a, __fp16 b, __fp16 c)
- {
-   swap (b, a);
-   return c;
- }
--- 0 ----
diff -Nrcpad gcc-14-20250912/gcc/testsuite/gcc.target/arm/fp16-aapcs.c gcc-14-20250919/gcc/testsuite/gcc.target/arm/fp16-aapcs.c
*** gcc-14-20250912/gcc/testsuite/gcc.target/arm/fp16-aapcs.c	Thu Jan  1 00:00:00 1970
--- gcc-14-20250919/gcc/testsuite/gcc.target/arm/fp16-aapcs.c	Fri Sep 19 22:32:52 2025
***************
*** 0 ****
--- 1,24 ----
+ /* { dg-do compile }  */
+ /* { dg-require-effective-target arm_fp16_alternative_ok } */
+ /* { dg-options "-O2" }  */
+ /* { dg-add-options arm_fp16_alternative } */
+ /* { dg-final { check-function-bodies "**" "" "" } } */
+ 
+ /* Test __fp16 arguments and return value in registers.  */
+ 
+ __fp16 f();
+ void g(__fp16);
+ void h();
+ 
+ /*
+ ** test:
+ ** ...
+ **	bl	f
+ **	bl	g
+ ** ...
+ */
+ int test()
+ {
+     g(f());
+     h();
+ }
diff -Nrcpad gcc-14-20250912/gcc/testsuite/gcc.target/i386/pieces-memcpy-18.c gcc-14-20250919/gcc/testsuite/gcc.target/i386/pieces-memcpy-18.c
*** gcc-14-20250912/gcc/testsuite/gcc.target/i386/pieces-memcpy-18.c	Fri Sep 12 22:32:17 2025
--- gcc-14-20250919/gcc/testsuite/gcc.target/i386/pieces-memcpy-18.c	Fri Sep 19 22:32:58 2025
***************
*** 1,5 ****
  /* { dg-do compile } */
! /* { dg-options "-O2 -march=sapphirerapids" } */
  
  extern char *dst, *src;
  
--- 1,5 ----
  /* { dg-do compile } */
! /* { dg-options "-O2 -march=znver5" } */
  
  extern char *dst, *src;
  
diff -Nrcpad gcc-14-20250912/gcc/testsuite/gcc.target/i386/pieces-memcpy-21.c gcc-14-20250919/gcc/testsuite/gcc.target/i386/pieces-memcpy-21.c
*** gcc-14-20250912/gcc/testsuite/gcc.target/i386/pieces-memcpy-21.c	Fri Sep 12 22:32:17 2025
--- gcc-14-20250919/gcc/testsuite/gcc.target/i386/pieces-memcpy-21.c	Fri Sep 19 22:32:58 2025
***************
*** 1,5 ****
  /* { dg-do compile } */
! /* { dg-options "-O2 -mtune=sapphirerapids -march=x86-64 -mavx2" } */
  
  extern char *dst, *src;
  
--- 1,5 ----
  /* { dg-do compile } */
! /* { dg-options "-O2 -mtune=znver5 -march=x86-64 -mavx2" } */
  
  extern char *dst, *src;
  
diff -Nrcpad gcc-14-20250912/gcc/testsuite/gcc.target/i386/pieces-memset-46.c gcc-14-20250919/gcc/testsuite/gcc.target/i386/pieces-memset-46.c
*** gcc-14-20250912/gcc/testsuite/gcc.target/i386/pieces-memset-46.c	Fri Sep 12 22:32:17 2025
--- gcc-14-20250919/gcc/testsuite/gcc.target/i386/pieces-memset-46.c	Fri Sep 19 22:32:58 2025
***************
*** 1,5 ****
  /* { dg-do compile } */
! /* { dg-options "-O2 -march=sapphirerapids" } */
  
  extern char *dst;
  
--- 1,5 ----
  /* { dg-do compile } */
! /* { dg-options "-O2 -march=znver5" } */
  
  extern char *dst;
  
diff -Nrcpad gcc-14-20250912/gcc/testsuite/gcc.target/i386/pieces-memset-49.c gcc-14-20250919/gcc/testsuite/gcc.target/i386/pieces-memset-49.c
*** gcc-14-20250912/gcc/testsuite/gcc.target/i386/pieces-memset-49.c	Fri Sep 12 22:32:17 2025
--- gcc-14-20250919/gcc/testsuite/gcc.target/i386/pieces-memset-49.c	Fri Sep 19 22:32:58 2025
***************
*** 1,5 ****
  /* { dg-do compile } */
! /* { dg-options "-O2 -mtune=sapphirerapids -march=x86-64 -mavx2" } */
  
  extern char *dst;
  
--- 1,5 ----
  /* { dg-do compile } */
! /* { dg-options "-O2 -mtune=znver5 -march=x86-64 -mavx2" } */
  
  extern char *dst;
  
diff -Nrcpad gcc-14-20250912/gcc/testsuite/gcc.target/s390/vector/vec-cmp-emu-1.c gcc-14-20250919/gcc/testsuite/gcc.target/s390/vector/vec-cmp-emu-1.c
*** gcc-14-20250912/gcc/testsuite/gcc.target/s390/vector/vec-cmp-emu-1.c	Thu Jan  1 00:00:00 1970
--- gcc-14-20250919/gcc/testsuite/gcc.target/s390/vector/vec-cmp-emu-1.c	Fri Sep 19 22:33:04 2025
***************
*** 0 ****
--- 1,35 ----
+ /* { dg-do compile } */
+ /* { dg-options "-O2 -mzarch -march=z13" } */
+ /* { dg-require-effective-target int128 } */
+ /* { dg-final { check-function-bodies "**" "" "" } } */
+ 
+ typedef __attribute__ ((vector_size (16))) signed __int128 v1ti;
+ typedef __attribute__ ((vector_size (16))) unsigned __int128 uv1ti;
+ 
+ /*
+ ** eq:
+ **	vceqg	(%v[0-9]+),%v[0-9]+,%v[0-9]+
+ **	vpdi	(%v[0-9]+),\1,\1,4
+ **	vn	%v24,(\1,\2|\2,\1)
+ **	br	%r14
+ */
+ 
+ v1ti
+ eq (v1ti x, v1ti y)
+ {
+   return x == y;
+ }
+ 
+ /*
+ ** ueq:
+ **	vceqg	(%v[0-9]+),%v[0-9]+,%v[0-9]+
+ **	vpdi	(%v[0-9]+),\1,\1,4
+ **	vn	%v24,(\1,\2|\2,\1)
+ **	br	%r14
+ */
+ 
+ uv1ti
+ ueq (uv1ti x, uv1ti y)
+ {
+   return x == y;
+ }
diff -Nrcpad gcc-14-20250912/gcc/testsuite/gcc.target/s390/vector/vec-cmp-emu-2.c gcc-14-20250919/gcc/testsuite/gcc.target/s390/vector/vec-cmp-emu-2.c
*** gcc-14-20250912/gcc/testsuite/gcc.target/s390/vector/vec-cmp-emu-2.c	Thu Jan  1 00:00:00 1970
--- gcc-14-20250919/gcc/testsuite/gcc.target/s390/vector/vec-cmp-emu-2.c	Fri Sep 19 22:33:04 2025
***************
*** 0 ****
--- 1,18 ----
+ /* { dg-do compile } */
+ /* { dg-options "-O3 -mzarch -march=z13" } */
+ /* { dg-require-effective-target int128 } */
+ /* { dg-final { scan-assembler-times {\tvchg\t} 1 } } */
+ /* { dg-final { scan-assembler-times {\tvchlg\t} 1 } } */
+ /* { dg-final { scan-assembler-times {\tvceqg\t} 1 } } */
+ /* { dg-final { scan-assembler-times {\tvpdi\t} 1 } } */
+ /* { dg-final { scan-assembler-times {\tvn\t} 1 } } */
+ /* { dg-final { scan-assembler-times {\tvo\t} 1 } } */
+ /* { dg-final { scan-assembler-times {\tvrepg\t} 1 } } */
+ 
+ typedef __attribute__ ((vector_size (16))) __int128 v1ti;
+ 
+ v1ti
+ gt (v1ti x, v1ti y)
+ {
+   return x > y;
+ }
diff -Nrcpad gcc-14-20250912/gcc/testsuite/gcc.target/s390/vector/vec-cmp-emu-3.c gcc-14-20250919/gcc/testsuite/gcc.target/s390/vector/vec-cmp-emu-3.c
*** gcc-14-20250912/gcc/testsuite/gcc.target/s390/vector/vec-cmp-emu-3.c	Thu Jan  1 00:00:00 1970
--- gcc-14-20250919/gcc/testsuite/gcc.target/s390/vector/vec-cmp-emu-3.c	Fri Sep 19 22:33:04 2025
***************
*** 0 ****
--- 1,17 ----
+ /* { dg-do compile } */
+ /* { dg-options "-O3 -mzarch -march=z13" } */
+ /* { dg-require-effective-target int128 } */
+ /* { dg-final { scan-assembler-times {\tvchlg\t} 1 } } */
+ /* { dg-final { scan-assembler-times {\tvceqg\t} 1 } } */
+ /* { dg-final { scan-assembler-times {\tvpdi\t} 1 } } */
+ /* { dg-final { scan-assembler-times {\tvn\t} 1 } } */
+ /* { dg-final { scan-assembler-times {\tvo\t} 1 } } */
+ /* { dg-final { scan-assembler-times {\tvrepg\t} 1 } } */
+ 
+ typedef __attribute__ ((vector_size (16))) unsigned __int128 uv1ti;
+ 
+ uv1ti
+ gt (uv1ti x, uv1ti y)
+ {
+   return x > y;
+ }
diff -Nrcpad gcc-14-20250912/libstdc++-v3/ChangeLog gcc-14-20250919/libstdc++-v3/ChangeLog
*** gcc-14-20250912/libstdc++-v3/ChangeLog	Fri Sep 12 22:32:27 2025
--- gcc-14-20250919/libstdc++-v3/ChangeLog	Fri Sep 19 22:33:13 2025
***************
*** 1,3 ****
--- 1,19 ----
+ 2025-09-15  Jonathan Wakely  <jwakely@redhat.com>
+ 
+ 	Backported from master:
+ 	2025-09-12  Jonathan Wakely  <jwakely@redhat.com>
+ 
+ 	PR libstdc++/117276
+ 	* include/pstl/parallel_backend_tbb.h (__func_task::finalize):
+ 	Make deallocation unconditional.
+ 
+ 2025-09-15  Jonathan Wakely  <jwakely@redhat.com>
+ 
+ 	Backported from master:
+ 	2025-09-10  Jonathan Wakely  <jwakely@redhat.com>
+ 
+ 	* include/bits/unique_ptr.h: Remove blank line.
+ 
  2025-09-09  Tomasz Kamiński  <tkaminsk@redhat.com>
  
  	Backported from master:
diff -Nrcpad gcc-14-20250912/libstdc++-v3/include/bits/unique_ptr.h gcc-14-20250919/libstdc++-v3/include/bits/unique_ptr.h
*** gcc-14-20250912/libstdc++-v3/include/bits/unique_ptr.h	Fri Sep 12 22:32:27 2025
--- gcc-14-20250919/libstdc++-v3/include/bits/unique_ptr.h	Fri Sep 19 22:33:14 2025
***************
*** 1,4 ****
- 
  // unique_ptr implementation -*- C++ -*-
  
  // Copyright (C) 2008-2024 Free Software Foundation, Inc.
--- 1,3 ----
diff -Nrcpad gcc-14-20250912/libstdc++-v3/include/pstl/parallel_backend_tbb.h gcc-14-20250919/libstdc++-v3/include/pstl/parallel_backend_tbb.h
*** gcc-14-20250912/libstdc++-v3/include/pstl/parallel_backend_tbb.h	Fri Sep 12 22:32:27 2025
--- gcc-14-20250919/libstdc++-v3/include/pstl/parallel_backend_tbb.h	Fri Sep 19 22:33:14 2025
*************** class __root_task
*** 521,527 ****
      friend class __func_task<_Func>;
  };
  
! #else  // TBB_INTERFACE_VERSION <= 12000
  class __task : public tbb::detail::d1::task
  {
    protected:
--- 521,527 ----
      friend class __func_task<_Func>;
  };
  
! #else  // TBB_INTERFACE_VERSION > 12000
  class __task : public tbb::detail::d1::task
  {
    protected:
*************** class __func_task : public __task
*** 656,665 ****
  
          _PSTL_ASSERT(__parent != nullptr);
          _PSTL_ASSERT(__parent->_M_refcount.load(std::memory_order_relaxed) > 0);
!         if (--__parent->_M_refcount == 0)
          {
              _PSTL_ASSERT(__next == nullptr);
-             __alloc.deallocate(this, *__ed);
              return __parent;
          }
  
--- 656,671 ----
  
          _PSTL_ASSERT(__parent != nullptr);
          _PSTL_ASSERT(__parent->_M_refcount.load(std::memory_order_relaxed) > 0);
! 
!         auto __refcount = --__parent->_M_refcount;
! 
!         // Placing the deallocation after the refcount decrement allows another thread to proceed with tree
!         // folding concurrently with this task cleanup.
!         __alloc.deallocate(this, *__ed);
! 
!         if (__refcount == 0)
          {
              _PSTL_ASSERT(__next == nullptr);
              return __parent;
          }
  
