diff -Nrcpad gcc-15-20250913/LAST_UPDATED gcc-15-20250920/LAST_UPDATED
*** gcc-15-20250913/LAST_UPDATED	Sat Sep 13 22:33:17 2025
--- gcc-15-20250920/LAST_UPDATED	Sat Sep 20 22:34:12 2025
***************
*** 1 ****
! Obtained from git: releases/gcc-15 revision 69d54b04b54de1090eb04734bd64ae42e8faaead
--- 1 ----
! Obtained from git: releases/gcc-15 revision 84e2023455a0180c9b6420bac5bdeec0041529b0
diff -Nrcpad gcc-15-20250913/MD5SUMS gcc-15-20250920/MD5SUMS
*** gcc-15-20250913/MD5SUMS	Sat Sep 13 22:33:21 2025
--- gcc-15-20250920/MD5SUMS	Sat Sep 20 22:34:16 2025
***************
*** 1,5 ****
  # This file contains the MD5 checksums of the files in the
! # gcc-15-20250913.tar.xz tarball.
  #
  # Besides verifying that all files in the tarball were correctly expanded,
  # it also can be used to determine if any files have changed since the
--- 1,5 ----
  # This file contains the MD5 checksums of the files in the
! # gcc-15-20250920.tar.xz tarball.
  #
  # Besides verifying that all files in the tarball were correctly expanded,
  # it also can be used to determine if any files have changed since the
*************** d32239bcb673463ab874e80d47fae504  COPYIN
*** 25,31 ****
  fd4ecdf5d672efe2b0e409aca9cf9446  ChangeLog.jit
  09538b708302f1735f6fa05b622ecf5e  ChangeLog.tree-ssa
  24ab760126489e69436a43185dc3d202  INSTALL/README
! 9f3bd8f732ebd333f015996de5020f96  LAST_UPDATED
  9d2cf5b58292c2e8b0804d3eafc2d6f3  MAINTAINERS
  b714b83dd28679b75c5fd3e619d35956  Makefile.def
  9d0808afc70085c5ca8d45062fc59689  Makefile.in
--- 25,31 ----
  fd4ecdf5d672efe2b0e409aca9cf9446  ChangeLog.jit
  09538b708302f1735f6fa05b622ecf5e  ChangeLog.tree-ssa
  24ab760126489e69436a43185dc3d202  INSTALL/README
! 65c10b0c1eb245ae8c6fac21f12a5f65  LAST_UPDATED
  9d2cf5b58292c2e8b0804d3eafc2d6f3  MAINTAINERS
  b714b83dd28679b75c5fd3e619d35956  Makefile.def
  9d0808afc70085c5ca8d45062fc59689  Makefile.in
*************** a22e70b3f29292d0e628450f4bb11e62  fixinc
*** 514,520 ****
  a916467b91076e631dd8edb7424769c7  gcc/COPYING.LIB
  d32239bcb673463ab874e80d47fae504  gcc/COPYING3
  6a6a8e020838b23406c81b19c1d46df6  gcc/COPYING3.LIB
! 6b1807c075ec6323c389196da20ffb6a  gcc/ChangeLog
  51281e73aa07fb62394bd72f3c9299ba  gcc/ChangeLog-1997
  f77af8c9ac412064886b00c5506123b5  gcc/ChangeLog-1998
  00a2e4ead1b289bf69bca0196fed6f9f  gcc/ChangeLog-1999
--- 514,520 ----
  a916467b91076e631dd8edb7424769c7  gcc/COPYING.LIB
  d32239bcb673463ab874e80d47fae504  gcc/COPYING3
  6a6a8e020838b23406c81b19c1d46df6  gcc/COPYING3.LIB
! ac2fe51cd206d8cace80969fc8a698f7  gcc/ChangeLog
  51281e73aa07fb62394bd72f3c9299ba  gcc/ChangeLog-1997
  f77af8c9ac412064886b00c5506123b5  gcc/ChangeLog-1998
  00a2e4ead1b289bf69bca0196fed6f9f  gcc/ChangeLog-1999
*************** fb3fadb88e1d2b3b640cfaaa5ff11780  gcc/Ch
*** 551,557 ****
  3eb07e0b2e542409bf73d359f7f65609  gcc/ChangeLog.ptr
  e13638e26743ba41e6011b76cc00d9a9  gcc/ChangeLog.tree-ssa
  739ab47f6425bcea1d05e4fc0542de54  gcc/ChangeLog.tuples
! 37e20aa55a96d543c1709561230aadee  gcc/DATESTAMP
  d41d8cd98f00b204e9800998ecf8427e  gcc/DEV-PHASE
  eb92e1ff5e982ca07e173e0eb286d243  gcc/FSFChangeLog
  30e1e33411566388b3164558482dc5e6  gcc/FSFChangeLog.10
--- 551,557 ----
  3eb07e0b2e542409bf73d359f7f65609  gcc/ChangeLog.ptr
  e13638e26743ba41e6011b76cc00d9a9  gcc/ChangeLog.tree-ssa
  739ab47f6425bcea1d05e4fc0542de54  gcc/ChangeLog.tuples
! 87b139ccc66abe9229e0db6969969195  gcc/DATESTAMP
  d41d8cd98f00b204e9800998ecf8427e  gcc/DEV-PHASE
  eb92e1ff5e982ca07e173e0eb286d243  gcc/FSFChangeLog
  30e1e33411566388b3164558482dc5e6  gcc/FSFChangeLog.10
*************** ec6799501b2eb2923d5de6a66169dbd2  gcc/ON
*** 563,569 ****
  cd96bf34cb76c97f86704a59b9ddb18a  gcc/acinclude.m4
  18db4664d7e31002aac43ebcf20e075f  gcc/aclocal.m4
  16a499934b71eb6cf7c0d6899cd6006a  gcc/ada/.gitignore
! 9ac60b4a1499cd09d568ba4e831ec444  gcc/ada/ChangeLog
  c2094c0d3135f9ac89917f162046ee04  gcc/ada/ChangeLog-2001
  fa410b57f5d814d5d3ac3b45f486cdcf  gcc/ada/ChangeLog-2002
  2dbefa7bdc8dc28ec746002028861278  gcc/ada/ChangeLog-2003
--- 563,569 ----
  cd96bf34cb76c97f86704a59b9ddb18a  gcc/acinclude.m4
  18db4664d7e31002aac43ebcf20e075f  gcc/aclocal.m4
  16a499934b71eb6cf7c0d6899cd6006a  gcc/ada/.gitignore
! 87b79c833e11ef2c46e374982b932833  gcc/ada/ChangeLog
  c2094c0d3135f9ac89917f162046ee04  gcc/ada/ChangeLog-2001
  fa410b57f5d814d5d3ac3b45f486cdcf  gcc/ada/ChangeLog-2002
  2dbefa7bdc8dc28ec746002028861278  gcc/ada/ChangeLog-2003
*************** ae344bff4834b9e2ef3c07f6dd01b59b  gcc/ad
*** 653,659 ****
  530290230985903c593cb9d92f5b47c8  gcc/ada/cal.c
  2acfb74c50c4563afcbe6a1bca3912a3  gcc/ada/casing.adb
  c576df64e1d6a2ac70b389cc10a835e6  gcc/ada/casing.ads
! 20d0c21e346ef575a30e5da2f84b9b97  gcc/ada/checks.adb
  f963647952269416533799c6a5117ea3  gcc/ada/checks.ads
  4c0942bba88f786dffff9a3575759026  gcc/ada/cio.c
  f14d5e59f3344d9d8ee8a0e5e48a7080  gcc/ada/clean.adb
--- 653,659 ----
  530290230985903c593cb9d92f5b47c8  gcc/ada/cal.c
  2acfb74c50c4563afcbe6a1bca3912a3  gcc/ada/casing.adb
  c576df64e1d6a2ac70b389cc10a835e6  gcc/ada/casing.ads
! de196fcd8bfd5f24501056cf73eb36fb  gcc/ada/checks.adb
  f963647952269416533799c6a5117ea3  gcc/ada/checks.ads
  4c0942bba88f786dffff9a3575759026  gcc/ada/cio.c
  f14d5e59f3344d9d8ee8a0e5e48a7080  gcc/ada/clean.adb
*************** b042ff9582cb94caab7f476203ea6809  gcc/ad
*** 818,824 ****
  52a5741c37559d0398594d7baa1c99ac  gcc/ada/exp_tss.ads
  17c1e6db56a29cef37eb0acfa2e2176f  gcc/ada/exp_unst.adb
  d2f34876e61000e49299ef9b2569cbbf  gcc/ada/exp_unst.ads
! e0890410b45b81ec10bec8de64107e53  gcc/ada/exp_util.adb
  f38c33811ff4495921f4fab803f1b045  gcc/ada/exp_util.ads
  3bba6a658c16a14ec3297c802dcde881  gcc/ada/expander.adb
  53bb0eb5c4feebf8b5fbef639f5827bd  gcc/ada/expander.ads
--- 818,824 ----
  52a5741c37559d0398594d7baa1c99ac  gcc/ada/exp_tss.ads
  17c1e6db56a29cef37eb0acfa2e2176f  gcc/ada/exp_unst.adb
  d2f34876e61000e49299ef9b2569cbbf  gcc/ada/exp_unst.ads
! b693cfb2d28222cc04921d80a58ffa9a  gcc/ada/exp_util.adb
  f38c33811ff4495921f4fab803f1b045  gcc/ada/exp_util.ads
  3bba6a658c16a14ec3297c802dcde881  gcc/ada/expander.adb
  53bb0eb5c4feebf8b5fbef639f5827bd  gcc/ada/expander.ads
*************** fa1feb51010fc73b933487acbdcf85e8  gcc/ad
*** 855,861 ****
  e8ba734d63b4001c905ea24a0dc1b6a3  gcc/ada/gcc-interface/misc.cc
  a74b4504c5ad4ed4e963f0691c289b40  gcc/ada/gcc-interface/system.ads
  b350a6fd65cafe8bd47dc42192437310  gcc/ada/gcc-interface/targtyps.cc
! b013e2da3e3d01faaf91e494bb26983e  gcc/ada/gcc-interface/trans.cc
  e8e1dea48e7ee6c84d438db1b4a6a9b2  gcc/ada/gcc-interface/utils.cc
  7b0d708fd189018a87468ef844fc3811  gcc/ada/gcc-interface/utils2.cc
  20ab1d2ee73423b8b0fababbae54659c  gcc/ada/gen_il-fields.ads
--- 855,861 ----
  e8ba734d63b4001c905ea24a0dc1b6a3  gcc/ada/gcc-interface/misc.cc
  a74b4504c5ad4ed4e963f0691c289b40  gcc/ada/gcc-interface/system.ads
  b350a6fd65cafe8bd47dc42192437310  gcc/ada/gcc-interface/targtyps.cc
! da03d35f4d69ea6f735edce7df124c15  gcc/ada/gcc-interface/trans.cc
  e8e1dea48e7ee6c84d438db1b4a6a9b2  gcc/ada/gcc-interface/utils.cc
  7b0d708fd189018a87468ef844fc3811  gcc/ada/gcc-interface/utils2.cc
  20ab1d2ee73423b8b0fababbae54659c  gcc/ada/gen_il-fields.ads
*************** d9450e0fa15cd8b8f6659555820ec24e  gcc/co
*** 3456,3462 ****
  7cfa3d0cdd28cdcd73a29c2c8a925548  gcc/config/aarch64/aarch64-simd-builtin-types.def
  f28e7beab7cc8baa0b1a2e5e9efc0597  gcc/config/aarch64/aarch64-simd-builtins.def
  33ce4a896b77324d9be6448637daf9ca  gcc/config/aarch64/aarch64-simd-pragma-builtins.def
! 289754bc9c6eb2b3ec2ebb609d36de73  gcc/config/aarch64/aarch64-simd.md
  400cf23fe3c345ede58d2194530c6231  gcc/config/aarch64/aarch64-sme.md
  221b858bba4517a3871cb07292c6b216  gcc/config/aarch64/aarch64-speculation.cc
  cab9211ac73c7480b9b4b45833e20d71  gcc/config/aarch64/aarch64-sve-builtins-base.cc
--- 3456,3462 ----
  7cfa3d0cdd28cdcd73a29c2c8a925548  gcc/config/aarch64/aarch64-simd-builtin-types.def
  f28e7beab7cc8baa0b1a2e5e9efc0597  gcc/config/aarch64/aarch64-simd-builtins.def
  33ce4a896b77324d9be6448637daf9ca  gcc/config/aarch64/aarch64-simd-pragma-builtins.def
! 40522c65acf5350dc270749770ecb25e  gcc/config/aarch64/aarch64-simd.md
  400cf23fe3c345ede58d2194530c6231  gcc/config/aarch64/aarch64-sme.md
  221b858bba4517a3871cb07292c6b216  gcc/config/aarch64/aarch64-speculation.cc
  cab9211ac73c7480b9b4b45833e20d71  gcc/config/aarch64/aarch64-sve-builtins-base.cc
*************** e055c97bc39ff21701576ecf45b3a7a0  gcc/co
*** 3471,3477 ****
  d90362e92083076dd19c9edc16b0600a  gcc/config/aarch64/aarch64-sve-builtins-sve2.cc
  5249e3dd61e8bd70c85a23c5711f3ca2  gcc/config/aarch64/aarch64-sve-builtins-sve2.def
  e2d80b89552da0c6b4cb6bede3b2e573  gcc/config/aarch64/aarch64-sve-builtins-sve2.h
! c3c4eb36575f25af5b1e1dc06de29dc0  gcc/config/aarch64/aarch64-sve-builtins.cc
  30d08305d5bc784af521254aea449949  gcc/config/aarch64/aarch64-sve-builtins.def
  5ef25fd86c1c16a4a6fb3f74e12802b4  gcc/config/aarch64/aarch64-sve-builtins.h
  f8e53efb41228263faa63280df0a8217  gcc/config/aarch64/aarch64-sve.md
--- 3471,3477 ----
  d90362e92083076dd19c9edc16b0600a  gcc/config/aarch64/aarch64-sve-builtins-sve2.cc
  5249e3dd61e8bd70c85a23c5711f3ca2  gcc/config/aarch64/aarch64-sve-builtins-sve2.def
  e2d80b89552da0c6b4cb6bede3b2e573  gcc/config/aarch64/aarch64-sve-builtins-sve2.h
! 37f3a64d71f21a6c7787399ca225b6b9  gcc/config/aarch64/aarch64-sve-builtins.cc
  30d08305d5bc784af521254aea449949  gcc/config/aarch64/aarch64-sve-builtins.def
  5ef25fd86c1c16a4a6fb3f74e12802b4  gcc/config/aarch64/aarch64-sve-builtins.h
  f8e53efb41228263faa63280df0a8217  gcc/config/aarch64/aarch64-sve.md
*************** f713d33fdaee532813b56547dd070c8c  gcc/co
*** 3506,3512 ****
  dfcdbda4a3bb64a86fdf64ce6fce0ae3  gcc/config/aarch64/geniterators.sh
  bc3b4ebfac8bfd42d3e9098f33585afd  gcc/config/aarch64/gentune.sh
  86eaf33edeb885c2c9ae2a9825879e59  gcc/config/aarch64/host-aarch64-darwin.cc
! ec99f43124343861723fa6a423e2b319  gcc/config/aarch64/iterators.md
  5b5a63a020088c423711fc910c09f55c  gcc/config/aarch64/predicates.md
  a4e902ee1494ba5eee811ea46ecdf995  gcc/config/aarch64/rtems.h
  9a62f0d5ab77ee226f2c440e8c4d3a1d  gcc/config/aarch64/t-aarch64
--- 3506,3512 ----
  dfcdbda4a3bb64a86fdf64ce6fce0ae3  gcc/config/aarch64/geniterators.sh
  bc3b4ebfac8bfd42d3e9098f33585afd  gcc/config/aarch64/gentune.sh
  86eaf33edeb885c2c9ae2a9825879e59  gcc/config/aarch64/host-aarch64-darwin.cc
! ebd811f0ed77e411e6941236371bd33b  gcc/config/aarch64/iterators.md
  5b5a63a020088c423711fc910c09f55c  gcc/config/aarch64/predicates.md
  a4e902ee1494ba5eee811ea46ecdf995  gcc/config/aarch64/rtems.h
  9a62f0d5ab77ee226f2c440e8c4d3a1d  gcc/config/aarch64/t-aarch64
*************** f805d118929dd79f6bd4dc75c77c968b  gcc/co
*** 3657,3663 ****
  a16ca2ab73b09afe4481044ebcec2010  gcc/config/arm/arm-tune.md
  7d95ec920300fa051646557add91f019  gcc/config/arm/arm.cc
  fe5e2b24f803c40d73fe860e114fc6e0  gcc/config/arm/arm.h
! 11e0d112671b369f4d182ac9d5c6066b  gcc/config/arm/arm.md
  a7974fb16c914604eacaf43120b8769f  gcc/config/arm/arm.opt
  d96083967a30e6eb0f75d624af2d831a  gcc/config/arm/arm.opt.urls
  ccbf8aa9582c7ea8db0ed6a70d1dd691  gcc/config/arm/arm1020e.md
--- 3657,3663 ----
  a16ca2ab73b09afe4481044ebcec2010  gcc/config/arm/arm-tune.md
  7d95ec920300fa051646557add91f019  gcc/config/arm/arm.cc
  fe5e2b24f803c40d73fe860e114fc6e0  gcc/config/arm/arm.h
! ebe671635930c4c0d2e57d5db9de57bf  gcc/config/arm/arm.md
  a7974fb16c914604eacaf43120b8769f  gcc/config/arm/arm.opt
  d96083967a30e6eb0f75d624af2d831a  gcc/config/arm/arm.opt.urls
  ccbf8aa9582c7ea8db0ed6a70d1dd691  gcc/config/arm/arm1020e.md
*************** fc218940ab265ae323b54d5f007d0d98  gcc/co
*** 3765,3771 ****
  5ed27daaa89e74cf4016168779065375  gcc/config/avr/avr-dimode.md
  a22b4318830a45fe7c7db53efb64970d  gcc/config/avr/avr-fixed.md
  f43b68e01b2d61fffb5336ef45fa1e7f  gcc/config/avr/avr-log.cc
! 117bbef05f3fb7ba16a92cee51e0064c  gcc/config/avr/avr-mcus.def
  1db4fe94056a22e92de33b6d365176c6  gcc/config/avr/avr-modes.def
  d37f092206fc4c0379cee5e5fc01b654  gcc/config/avr/avr-passes-fuse-move.h
  ce627f4de03a506a4263a68742891105  gcc/config/avr/avr-passes.cc
--- 3765,3771 ----
  5ed27daaa89e74cf4016168779065375  gcc/config/avr/avr-dimode.md
  a22b4318830a45fe7c7db53efb64970d  gcc/config/avr/avr-fixed.md
  f43b68e01b2d61fffb5336ef45fa1e7f  gcc/config/avr/avr-log.cc
! 16c38242d01a11655dde3f3dafd49a17  gcc/config/avr/avr-mcus.def
  1db4fe94056a22e92de33b6d365176c6  gcc/config/avr/avr-modes.def
  d37f092206fc4c0379cee5e5fc01b654  gcc/config/avr/avr-passes-fuse-move.h
  ce627f4de03a506a4263a68742891105  gcc/config/avr/avr-passes.cc
*************** d4774d1c1bf66446a29da4693ee53d1e  gcc/co
*** 4318,4324 ****
  acfa3e6ce1f37bbad35e49e06b663ea9  gcc/config/i386/x86-tune-sched-bd.cc
  13fcb5234b2d8208c12932d96efef72b  gcc/config/i386/x86-tune-sched-core.cc
  9054e39f9f68ade31cfdeb33e9c905ce  gcc/config/i386/x86-tune-sched.cc
! 29d864447ea152baac4880e98ba5796f  gcc/config/i386/x86-tune.def
  95b91fd21504348ecd2f8510ebab204c  gcc/config/i386/x86gprintrin.h
  1ef1746c703bfdb9c245f7b7276b7d56  gcc/config/i386/x86intrin.h
  709155b5a0371d397baf22295493b77b  gcc/config/i386/xm-cygwin.h
--- 4318,4324 ----
  acfa3e6ce1f37bbad35e49e06b663ea9  gcc/config/i386/x86-tune-sched-bd.cc
  13fcb5234b2d8208c12932d96efef72b  gcc/config/i386/x86-tune-sched-core.cc
  9054e39f9f68ade31cfdeb33e9c905ce  gcc/config/i386/x86-tune-sched.cc
! 86d478728a40c7ddb0129282ee1e07b3  gcc/config/i386/x86-tune.def
  95b91fd21504348ecd2f8510ebab204c  gcc/config/i386/x86gprintrin.h
  1ef1746c703bfdb9c245f7b7276b7d56  gcc/config/i386/x86intrin.h
  709155b5a0371d397baf22295493b77b  gcc/config/i386/xm-cygwin.h
*************** a8cd9a4a3d712802475e91e0ec9a3274  gcc/co
*** 4438,4444 ****
  f539c2da7e8d7a3ef7c741bceee19eed  gcc/config/loongarch/loongarch-tune.h
  0b6b53c934d971c8e4f204caacf7f291  gcc/config/loongarch/loongarch.cc
  cac7a4f19361731647870d2210078a9e  gcc/config/loongarch/loongarch.h
! 9fd9109f20f7dfce6de910d45b5dbc85  gcc/config/loongarch/loongarch.md
  bcc951e237d5501fc2acd6ef3141724c  gcc/config/loongarch/loongarch.opt
  264f23ee79258ff82bda293d093dd06b  gcc/config/loongarch/loongarch.opt.urls
  a1ceaab52de5f1950f6c6b63c5a718ea  gcc/config/loongarch/lsx.md
--- 4438,4444 ----
  f539c2da7e8d7a3ef7c741bceee19eed  gcc/config/loongarch/loongarch-tune.h
  0b6b53c934d971c8e4f204caacf7f291  gcc/config/loongarch/loongarch.cc
  cac7a4f19361731647870d2210078a9e  gcc/config/loongarch/loongarch.h
! ec46785efb7afdd2deb34ce71a037c59  gcc/config/loongarch/loongarch.md
  bcc951e237d5501fc2acd6ef3141724c  gcc/config/loongarch/loongarch.opt
  264f23ee79258ff82bda293d093dd06b  gcc/config/loongarch/loongarch.opt.urls
  a1ceaab52de5f1950f6c6b63c5a718ea  gcc/config/loongarch/lsx.md
*************** cb26f6c0709fd9533aec72a07a36bf8b  gcc/co
*** 4539,4555 ****
  d2676839c4d7a7bcd706a386c029aea2  gcc/config/mcore/predicates.md
  8e427b88391a8cbadd500d5b5c18dd88  gcc/config/mcore/t-mcore
  899d399d572cb0f5b6983bf29e5f2dc1  gcc/config/microblaze/constraints.md
  cd06662d679aac52aa61b8507723384a  gcc/config/microblaze/linux.h
  9bc1818e3b430b758bafdf04bac27f5b  gcc/config/microblaze/microblaze-c.cc
! c1cdfa70252d5e45a9df69ddc7a1ddcb  gcc/config/microblaze/microblaze-protos.h
! b6ebd6ba65f7755a82057ecdf931d5aa  gcc/config/microblaze/microblaze.cc
  0a4fb603eb9a1c6e31bb8fa7e38b16d1  gcc/config/microblaze/microblaze.h
! b3a2d37f3594f70e239fba70728cc641  gcc/config/microblaze/microblaze.md
  3da1e85fbc11c0a5b746cb77b96a06f3  gcc/config/microblaze/microblaze.opt
  ab7ecb87ef3b7a388cab0e4d0d2eb0db  gcc/config/microblaze/microblaze.opt.urls
  0014185f2b662af11e97611027548662  gcc/config/microblaze/predicates.md
  6440a5281eac59ad82a11734d4e82b80  gcc/config/microblaze/rtems.h
! 17120f7b651cdd7f0ef24e2c1b93b29b  gcc/config/microblaze/sync.md
  df031372af9c825d21d2058d266247a0  gcc/config/microblaze/t-microblaze
  63ccba4e7f745d36609d7c129bac6288  gcc/config/microblaze/t-microblaze-linux
  a8b08640136e3e7712d2278eb84c21d9  gcc/config/microblaze/t-rtems
--- 4539,4556 ----
  d2676839c4d7a7bcd706a386c029aea2  gcc/config/mcore/predicates.md
  8e427b88391a8cbadd500d5b5c18dd88  gcc/config/mcore/t-mcore
  899d399d572cb0f5b6983bf29e5f2dc1  gcc/config/microblaze/constraints.md
+ 1ac49ffd4d6e30329a7a425da3ce8eaa  gcc/config/microblaze/iterators.md
  cd06662d679aac52aa61b8507723384a  gcc/config/microblaze/linux.h
  9bc1818e3b430b758bafdf04bac27f5b  gcc/config/microblaze/microblaze-c.cc
! 6e52b66a284ee7f7534fd34961907824  gcc/config/microblaze/microblaze-protos.h
! ad6bbf6b9c6de5a9c347d1cd48cc4c76  gcc/config/microblaze/microblaze.cc
  0a4fb603eb9a1c6e31bb8fa7e38b16d1  gcc/config/microblaze/microblaze.h
! 3af23e0040365b8a82498e8fd7e83bf5  gcc/config/microblaze/microblaze.md
  3da1e85fbc11c0a5b746cb77b96a06f3  gcc/config/microblaze/microblaze.opt
  ab7ecb87ef3b7a388cab0e4d0d2eb0db  gcc/config/microblaze/microblaze.opt.urls
  0014185f2b662af11e97611027548662  gcc/config/microblaze/predicates.md
  6440a5281eac59ad82a11734d4e82b80  gcc/config/microblaze/rtems.h
! 1750a4538fa32f377e18fb05173b0d21  gcc/config/microblaze/sync.md
  df031372af9c825d21d2058d266247a0  gcc/config/microblaze/t-microblaze
  63ccba4e7f745d36609d7c129bac6288  gcc/config/microblaze/t-microblaze-linux
  a8b08640136e3e7712d2278eb84c21d9  gcc/config/microblaze/t-rtems
*************** a9c3cddee4e237141062720b72fe38cd  gcc/co
*** 5498,5504 ****
  5d31df44fc0a5b17beb74ce0ff38e214  gcc/coroutine-passes.cc
  2a5216aefb9cdf4b270ef8e599cc794f  gcc/coverage.cc
  722fb5fda78e55c5af5da72cad78751f  gcc/coverage.h
! e10cded8aee0469d145d3118c170d4a2  gcc/cp/ChangeLog
  70c059f2b75a2fc1bb95a526b21b8cd7  gcc/cp/ChangeLog-1993
  7cbd106e10a0ba7c052bee3fe20671c2  gcc/cp/ChangeLog-1994
  3b1e3ed23ad4363f75e6fd2fbb583dee  gcc/cp/ChangeLog-1995
--- 5499,5505 ----
  5d31df44fc0a5b17beb74ce0ff38e214  gcc/coroutine-passes.cc
  2a5216aefb9cdf4b270ef8e599cc794f  gcc/coverage.cc
  722fb5fda78e55c5af5da72cad78751f  gcc/coverage.h
! ef5e03454fe12a6314221521048ff531  gcc/cp/ChangeLog
  70c059f2b75a2fc1bb95a526b21b8cd7  gcc/cp/ChangeLog-1993
  7cbd106e10a0ba7c052bee3fe20671c2  gcc/cp/ChangeLog-1994
  3b1e3ed23ad4363f75e6fd2fbb583dee  gcc/cp/ChangeLog-1995
*************** ddfea14bf3538c63472f984625d70840  gcc/cp
*** 5573,5579 ****
  ac5d78393361c1bcb930119a896a14ca  gcc/cp/lang-specs.h
  81021bc440a536664fa5365b475b36c5  gcc/cp/lex.cc
  aaf76a9b03fd0532d2904aef004fd66a  gcc/cp/logic.cc
! 397b8de2f52e596d7d76347ee016a9b4  gcc/cp/mangle.cc
  936bd061907a7a899c3285cf17b17674  gcc/cp/mapper-client.cc
  6c77b1fab5f6d146677090285a202a50  gcc/cp/mapper-client.h
  44e22b51797f89c9da996523a6d97f1c  gcc/cp/mapper-resolver.cc
--- 5574,5580 ----
  ac5d78393361c1bcb930119a896a14ca  gcc/cp/lang-specs.h
  81021bc440a536664fa5365b475b36c5  gcc/cp/lex.cc
  aaf76a9b03fd0532d2904aef004fd66a  gcc/cp/logic.cc
! c2a7409e57253e5d9bfd8ce29fb85212  gcc/cp/mangle.cc
  936bd061907a7a899c3285cf17b17674  gcc/cp/mapper-client.cc
  6c77b1fab5f6d146677090285a202a50  gcc/cp/mapper-client.h
  44e22b51797f89c9da996523a6d97f1c  gcc/cp/mapper-resolver.cc
*************** c61c4737f1261c516fd04ddbb16c545e  gcc/di
*** 5911,5917 ****
  bec68218d528467fd119bf2cd02bc358  gcc/digraph.cc
  18e73120a6e21ceac1adce40777000cf  gcc/digraph.h
  bb82bca6383082ead28f6f21f0a6223f  gcc/doc/analyzer.texi
! 7c6d6f8bba4a9890d950bdef623af96f  gcc/doc/avr-mmcu.texi
  628200aba31497f381052220465b8927  gcc/doc/bugreport.texi
  4f969d517229b2a96d02a2cc09fb85f1  gcc/doc/cfg.texi
  5c6f1e0d6b6424f27020c9e5c08807d4  gcc/doc/collect2.texi
--- 5912,5918 ----
  bec68218d528467fd119bf2cd02bc358  gcc/digraph.cc
  18e73120a6e21ceac1adce40777000cf  gcc/digraph.h
  bb82bca6383082ead28f6f21f0a6223f  gcc/doc/analyzer.texi
! 73b84511fa3199b1850b9f63c2f0f50e  gcc/doc/avr-mmcu.texi
  628200aba31497f381052220465b8927  gcc/doc/bugreport.texi
  4f969d517229b2a96d02a2cc09fb85f1  gcc/doc/cfg.texi
  5c6f1e0d6b6424f27020c9e5c08807d4  gcc/doc/collect2.texi
*************** ed475e0212369987bb572e7eabb4b4d7  gcc/lo
*** 6634,6640 ****
  05bf78e6d3e36587723b1177ffcd9c6e  gcc/lower-subreg.h
  755a196fed2cd7b5878159035d75b39b  gcc/lra-assigns.cc
  0232e051e662ebb7fd2fa507d9c581b8  gcc/lra-coalesce.cc
! 0a7f87d564757681bdd43429a8b86694  gcc/lra-constraints.cc
  90be6ca8eebfbeae80589ba7a895bf60  gcc/lra-eliminations.cc
  d5aab2fda62b4b8a67dcd1bfeff169f5  gcc/lra-int.h
  9b39c90253128330d1b238b030a40fce  gcc/lra-lives.cc
--- 6635,6641 ----
  05bf78e6d3e36587723b1177ffcd9c6e  gcc/lower-subreg.h
  755a196fed2cd7b5878159035d75b39b  gcc/lra-assigns.cc
  0232e051e662ebb7fd2fa507d9c581b8  gcc/lra-coalesce.cc
! 6f4946708c384630b0e1a23f12596d9b  gcc/lra-constraints.cc
  90be6ca8eebfbeae80589ba7a895bf60  gcc/lra-eliminations.cc
  d5aab2fda62b4b8a67dcd1bfeff169f5  gcc/lra-int.h
  9b39c90253128330d1b238b030a40fce  gcc/lra-lives.cc
*************** b1497a03867668af210c32280876fdd7  gcc/sy
*** 8445,8451 ****
  b4bbfe8a8f62eed5c75429762e88d324  gcc/targhooks.cc
  ae57260b8b60d8b8dfaef3556c3ac5e5  gcc/targhooks.h
  f39fcaa8197187283ccfed40107b426d  gcc/testsuite/.gitattributes
! 4f22905de5fe22c128d632b2b517debe  gcc/testsuite/ChangeLog
  47e8e29b649ead73b8a1e4797da470ed  gcc/testsuite/ChangeLog-1993-2007
  35198a9e4fd31b935de8789faabf3351  gcc/testsuite/ChangeLog-2008
  0f19934540750356d1b91595cebfd9a8  gcc/testsuite/ChangeLog-2009
--- 8446,8452 ----
  b4bbfe8a8f62eed5c75429762e88d324  gcc/targhooks.cc
  ae57260b8b60d8b8dfaef3556c3ac5e5  gcc/targhooks.h
  f39fcaa8197187283ccfed40107b426d  gcc/testsuite/.gitattributes
! a366940ef0579b5bf4c5da9f2472e1f7  gcc/testsuite/ChangeLog
  47e8e29b649ead73b8a1e4797da470ed  gcc/testsuite/ChangeLog-1993-2007
  35198a9e4fd31b935de8789faabf3351  gcc/testsuite/ChangeLog-2008
  0f19934540750356d1b91595cebfd9a8  gcc/testsuite/ChangeLog-2009
*************** b1579268264426b91fb29ca4a7ae6672  gcc/te
*** 15311,15316 ****
--- 15312,15318 ----
  ed79cf5bf3c45230ee9187c4cf51338e  gcc/testsuite/g++.dg/abi/packed1.C
  a6094bf319c105760bebe41768865b66  gcc/testsuite/g++.dg/abi/param1.C
  dc8d04461395fe21c8df3c3ddc0eaefb  gcc/testsuite/g++.dg/abi/param2.C
+ c6ee91a6fae5891b271cf08faea94bc7  gcc/testsuite/g++.dg/abi/pr121801.C
  4f8a99ff3fb06bd92fa2824ba0222b0d  gcc/testsuite/g++.dg/abi/pr39188-1.h
  0b334e68ad96b9b585797769690bad26  gcc/testsuite/g++.dg/abi/pr39188-1a.C
  c96cb62975d4855a114a03ac254e17ce  gcc/testsuite/g++.dg/abi/pr39188-1b.C
*************** eee3684fddf95ff5545c7c4454331e54  gcc/te
*** 62081,62086 ****
--- 62083,62089 ----
  7a8dbe7357968ea67da61dae6606ebcd  gcc/testsuite/gcc.target/aarch64/simd/mf8_data_2.c
  2f6c6fee34ced3b932053a03d9906520  gcc/testsuite/gcc.target/aarch64/simd/pr117048.c
  2797bd4410da16b66ebb2f474c595ee5  gcc/testsuite/gcc.target/aarch64/simd/pr117048_2.c
+ 67e9f00dffaa6f894241ef054cf29a1e  gcc/testsuite/gcc.target/aarch64/simd/pr121749.c
  f2791d55a2c9ed7182a54a406810cf47  gcc/testsuite/gcc.target/aarch64/simd/pr67896.c
  c4b08114012e09e0f47a84f5e5311441  gcc/testsuite/gcc.target/aarch64/simd/pr97349.c
  46d08ecc25480336a5b22ec204104ec5  gcc/testsuite/gcc.target/aarch64/simd/pr99195_1.c
*************** e716ac2dd0b6a489e0a066923531fe33  gcc/te
*** 64626,64639 ****
  a7a4c48a2a400e927d1783f11ff5ae2f  gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_lane_f16.c
  1c2f087197693ac0f8341bb2de2f9903  gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_lane_f32.c
  9bf80dcb14d6ec0ad3830bc283fafefa  gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_lane_f64.c
! 5819dc70d5a76c525b922277c0b959ee  gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s16.c
! 6a2ee9b11969c4475629e14cfed49038  gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s32.c
! a5cea13f4b457eccce848243008a2449  gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s64.c
! 540ce03a5aa12db4294f15800b60e830  gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s8.c
! 935cb2f781553ba0bbcf7db6a6443a26  gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u16.c
! d22a6497edd09e3536df77b5f96e55dd  gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u32.c
! 416804e673fcd9e4da8d4cbbe54e3099  gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u64.c
! 90173ee0d5de2d7ce44b254c077c25f6  gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u8.c
  13e5426577da8e8350426b98cdde0d0f  gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_s16.c
  887cde542b27dadbbd6e7abe7696d2cd  gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_s32.c
  78776c6e140b51a29713f2889bc58bca  gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_s64.c
--- 64629,64642 ----
  a7a4c48a2a400e927d1783f11ff5ae2f  gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_lane_f16.c
  1c2f087197693ac0f8341bb2de2f9903  gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_lane_f32.c
  9bf80dcb14d6ec0ad3830bc283fafefa  gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_lane_f64.c
! 93bec38f83aa08ea078a190a36ce60b6  gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s16.c
! 4f42232f407acd56314fee0d0ff008e5  gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s32.c
! 729ad62f6cb28217b9d2f1501b162f8c  gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s64.c
! 56c4878136209bdc3156de990353cecf  gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s8.c
! 6def2e7ca37494f570e330b41d18842f  gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u16.c
! 6993cbec8b136cc2cbabb54c90558144  gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u32.c
! 465a374b40b8fec960f6f658afb9e57b  gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u64.c
! 59e9a7a2c74e7a644223ce578131448e  gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u8.c
  13e5426577da8e8350426b98cdde0d0f  gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_s16.c
  887cde542b27dadbbd6e7abe7696d2cd  gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_s32.c
  78776c6e140b51a29713f2889bc58bca  gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_s64.c
*************** deee7c31c5c250e8d2a4897962cdea6b  gcc/te
*** 69111,69122 ****
  624f21c628f0db266ffbb61efa0744c4  gcc/testsuite/gcc.target/arm/acle/ldcl.c
  3bab4e19ec4b17521402dfe4ef493288  gcc/testsuite/gcc.target/arm/acle/mcr.c
  7762e55b0ca2ef639e394dcbf0310e9d  gcc/testsuite/gcc.target/arm/acle/mcr2.c
! 835054b801b16b5cdedbb209ce908545  gcc/testsuite/gcc.target/arm/acle/mcrr.c
! ad33a8d60b3b2cd3d4f1a464974118d3  gcc/testsuite/gcc.target/arm/acle/mcrr2.c
  eee783c37d90eef12bf5d89dd9e9f34c  gcc/testsuite/gcc.target/arm/acle/mrc.c
  1089abf6533526d82e14c2c80d726483  gcc/testsuite/gcc.target/arm/acle/mrc2.c
! e66b3819f1cc1c13b66c38b83972f3a2  gcc/testsuite/gcc.target/arm/acle/mrrc.c
! 5280b32decaf5622a9f85f834e828bdf  gcc/testsuite/gcc.target/arm/acle/mrrc2.c
  861a159d41b35397c6507e6d28db94f5  gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-1.c
  000e018d4a9cef746da9ce68f812b5d8  gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-10.c
  3b4d3eb19280d0960f628378b29198de  gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-11.c
--- 69114,69125 ----
  624f21c628f0db266ffbb61efa0744c4  gcc/testsuite/gcc.target/arm/acle/ldcl.c
  3bab4e19ec4b17521402dfe4ef493288  gcc/testsuite/gcc.target/arm/acle/mcr.c
  7762e55b0ca2ef639e394dcbf0310e9d  gcc/testsuite/gcc.target/arm/acle/mcr2.c
! dfd2b10cfdc1cd7abe9d9c7e78ce4524  gcc/testsuite/gcc.target/arm/acle/mcrr.c
! afda16d3c97c2103efa481403bc85b15  gcc/testsuite/gcc.target/arm/acle/mcrr2.c
  eee783c37d90eef12bf5d89dd9e9f34c  gcc/testsuite/gcc.target/arm/acle/mrc.c
  1089abf6533526d82e14c2c80d726483  gcc/testsuite/gcc.target/arm/acle/mrc2.c
! 8d93c83d44d4793e5a63a292987b3195  gcc/testsuite/gcc.target/arm/acle/mrrc.c
! 328ad16bf3e69ce775fb3225bd750980  gcc/testsuite/gcc.target/arm/acle/mrrc2.c
  861a159d41b35397c6507e6d28db94f5  gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-1.c
  000e018d4a9cef746da9ce68f812b5d8  gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-10.c
  3b4d3eb19280d0960f628378b29198de  gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-11.c
*************** e95ad2780e346935674e8e065a322d1d  gcc/te
*** 69459,69468 ****
  575ab2ac98e30ba3e1b351506a8afcb0  gcc/testsuite/gcc.target/arm/fmaxmin-2.c
  1f15e3fad418a20060c0b8a618fb5723  gcc/testsuite/gcc.target/arm/fmaxmin.c
  a1182e17a398d2114e6f9d6156618a24  gcc/testsuite/gcc.target/arm/fmaxmin.x
! acd3e91a7d28ee5546286c4936d86e11  gcc/testsuite/gcc.target/arm/fp16-aapcs-1.c
! 9e99c9ae7465a5459e190cb5d75fe5f7  gcc/testsuite/gcc.target/arm/fp16-aapcs-2.c
! 76aa061fcf894a1336f2f8d07bcd7524  gcc/testsuite/gcc.target/arm/fp16-aapcs-3.c
! 45400d3cc5277c10b804897e439d5ea8  gcc/testsuite/gcc.target/arm/fp16-aapcs-4.c
  f7e509420aab463592a3e5d54b6c6b8c  gcc/testsuite/gcc.target/arm/fp16-builtins-1.c
  237aa223257ca24bfddebcc43dd387a2  gcc/testsuite/gcc.target/arm/fp16-compile-alt-1.c
  85be9f1d24d495b2882fc58bb89a96d2  gcc/testsuite/gcc.target/arm/fp16-compile-alt-10.c
--- 69462,69468 ----
  575ab2ac98e30ba3e1b351506a8afcb0  gcc/testsuite/gcc.target/arm/fmaxmin-2.c
  1f15e3fad418a20060c0b8a618fb5723  gcc/testsuite/gcc.target/arm/fmaxmin.c
  a1182e17a398d2114e6f9d6156618a24  gcc/testsuite/gcc.target/arm/fmaxmin.x
! d8203dd017181ab133e278b2250a10d4  gcc/testsuite/gcc.target/arm/fp16-aapcs.c
  f7e509420aab463592a3e5d54b6c6b8c  gcc/testsuite/gcc.target/arm/fp16-builtins-1.c
  237aa223257ca24bfddebcc43dd387a2  gcc/testsuite/gcc.target/arm/fp16-compile-alt-1.c
  85be9f1d24d495b2882fc58bb89a96d2  gcc/testsuite/gcc.target/arm/fp16-compile-alt-10.c
*************** cbaafd43310e10a7ba4ce687bafe06da  gcc/te
*** 79229,79239 ****
  89d909d7d758041e829631ac800bf196  gcc/testsuite/gcc.target/i386/pieces-memcpy-15.c
  437a6c001b5f504cb8a978424f9f229c  gcc/testsuite/gcc.target/i386/pieces-memcpy-16.c
  a0fc0b89838032f850b17823a354b986  gcc/testsuite/gcc.target/i386/pieces-memcpy-17.c
! ce99ca62859e3b5ee0e5695b59309237  gcc/testsuite/gcc.target/i386/pieces-memcpy-18.c
  b5f6fb3aaac27e15ae52d9111e60d98d  gcc/testsuite/gcc.target/i386/pieces-memcpy-19.c
  279c04d20615905ca5bf2f44eb5a231d  gcc/testsuite/gcc.target/i386/pieces-memcpy-2.c
  7e2d486487e1f536c226d8bc290fd8ad  gcc/testsuite/gcc.target/i386/pieces-memcpy-20.c
! 2f4b551b9d6addea576cff08a8831f3f  gcc/testsuite/gcc.target/i386/pieces-memcpy-21.c
  483ed3c0a5b3efe685343cb5dc87d54d  gcc/testsuite/gcc.target/i386/pieces-memcpy-22.c
  2820c9b91ec98c38843764eea07d4b75  gcc/testsuite/gcc.target/i386/pieces-memcpy-3.c
  698986063dd5ba005476ca849de14359  gcc/testsuite/gcc.target/i386/pieces-memcpy-4.c
--- 79229,79239 ----
  89d909d7d758041e829631ac800bf196  gcc/testsuite/gcc.target/i386/pieces-memcpy-15.c
  437a6c001b5f504cb8a978424f9f229c  gcc/testsuite/gcc.target/i386/pieces-memcpy-16.c
  a0fc0b89838032f850b17823a354b986  gcc/testsuite/gcc.target/i386/pieces-memcpy-17.c
! 7a34703054f1d16fc3e3de2cc1b87012  gcc/testsuite/gcc.target/i386/pieces-memcpy-18.c
  b5f6fb3aaac27e15ae52d9111e60d98d  gcc/testsuite/gcc.target/i386/pieces-memcpy-19.c
  279c04d20615905ca5bf2f44eb5a231d  gcc/testsuite/gcc.target/i386/pieces-memcpy-2.c
  7e2d486487e1f536c226d8bc290fd8ad  gcc/testsuite/gcc.target/i386/pieces-memcpy-20.c
! 9d90237b50551a44a67d354724502ebb  gcc/testsuite/gcc.target/i386/pieces-memcpy-21.c
  483ed3c0a5b3efe685343cb5dc87d54d  gcc/testsuite/gcc.target/i386/pieces-memcpy-22.c
  2820c9b91ec98c38843764eea07d4b75  gcc/testsuite/gcc.target/i386/pieces-memcpy-3.c
  698986063dd5ba005476ca849de14359  gcc/testsuite/gcc.target/i386/pieces-memcpy-4.c
*************** ab6fa2bfe98c867fab182d157d457706  gcc/te
*** 79282,79291 ****
  d98f40e3e5aa8e8b9f5499569f688965  gcc/testsuite/gcc.target/i386/pieces-memset-43.c
  2b47b7f82aeabc7a238642520819b3f0  gcc/testsuite/gcc.target/i386/pieces-memset-44.c
  86947bff2a1eb3faba119670600994db  gcc/testsuite/gcc.target/i386/pieces-memset-45.c
! f29f6d2af05e1f08f148f0eed162d860  gcc/testsuite/gcc.target/i386/pieces-memset-46.c
  8f0614f1d8cbc09d9e6e515b9c85586c  gcc/testsuite/gcc.target/i386/pieces-memset-47.c
  fab4224ceed336ed6902793909c0c6c2  gcc/testsuite/gcc.target/i386/pieces-memset-48.c
! b6a5763cac2b72e43f0900c7fbca0740  gcc/testsuite/gcc.target/i386/pieces-memset-49.c
  e59e962761850423b307c01f720c8e84  gcc/testsuite/gcc.target/i386/pieces-memset-5.c
  f6afe5571570af54d1d2e02c0e28d3f6  gcc/testsuite/gcc.target/i386/pieces-memset-50.c
  587ca57e48d1c64f4cb91b6203512c99  gcc/testsuite/gcc.target/i386/pieces-memset-51.c
--- 79282,79291 ----
  d98f40e3e5aa8e8b9f5499569f688965  gcc/testsuite/gcc.target/i386/pieces-memset-43.c
  2b47b7f82aeabc7a238642520819b3f0  gcc/testsuite/gcc.target/i386/pieces-memset-44.c
  86947bff2a1eb3faba119670600994db  gcc/testsuite/gcc.target/i386/pieces-memset-45.c
! 3647374ee718421444609e296cfa0ad2  gcc/testsuite/gcc.target/i386/pieces-memset-46.c
  8f0614f1d8cbc09d9e6e515b9c85586c  gcc/testsuite/gcc.target/i386/pieces-memset-47.c
  fab4224ceed336ed6902793909c0c6c2  gcc/testsuite/gcc.target/i386/pieces-memset-48.c
! 9f2ed79a200ad2a71bf00d1e582aae79  gcc/testsuite/gcc.target/i386/pieces-memset-49.c
  e59e962761850423b307c01f720c8e84  gcc/testsuite/gcc.target/i386/pieces-memset-5.c
  f6afe5571570af54d1d2e02c0e28d3f6  gcc/testsuite/gcc.target/i386/pieces-memset-50.c
  587ca57e48d1c64f4cb91b6203512c99  gcc/testsuite/gcc.target/i386/pieces-memset-51.c
*************** dde2cba27bc4292492e4c0dd492a70e0  gcc/te
*** 83372,83377 ****
--- 83372,83378 ----
  359760e5160f4b52d2fa349806589a0d  gcc/testsuite/gcc.target/loongarch/pr121064.c
  acf1fac916847c2064b8d2bbb6535828  gcc/testsuite/gcc.target/loongarch/pr121542.c
  754f11f1533603a4d550b593afc0c673  gcc/testsuite/gcc.target/loongarch/pr121634.c
+ 1dd25b33f6fd8d4c4dc750865d86f404  gcc/testsuite/gcc.target/loongarch/pr121906.c
  1eac553341d725c6e59615b593aedb0d  gcc/testsuite/gcc.target/loongarch/pragma-push-pop.c
  3adba2a8ae6f671eb22ec8228777c1ac  gcc/testsuite/gcc.target/loongarch/prolog-opt.c
  1bfa30f99dc5f04f569fbff68640ab19  gcc/testsuite/gcc.target/loongarch/recip-divf.c
*************** d680e7307fb59fe24f8431e179191f16  libssp
*** 131883,131889 ****
  534c3fb4a88e5c1f70db35c12b7742c3  libssp/vsnprintf-chk.c
  34daeb04a522ee796098df4446d6ce61  libssp/vsprintf-chk.c
  9e2de2e1f20ab0ffa2201164de02824f  libstdc++-v3/.editorconfig
! ebcbeb4be91be9b8a4a47c3d6c100f70  libstdc++-v3/ChangeLog
  7aa6c40440a44fcf5ec94c066160c2f8  libstdc++-v3/ChangeLog-1998
  7aff86600b6a1ed3fa87305075a92db0  libstdc++-v3/ChangeLog-1999
  a6f28e8fc9bb07696a9e068b439a3a87  libstdc++-v3/ChangeLog-2000
--- 131884,131890 ----
  534c3fb4a88e5c1f70db35c12b7742c3  libssp/vsnprintf-chk.c
  34daeb04a522ee796098df4446d6ce61  libssp/vsprintf-chk.c
  9e2de2e1f20ab0ffa2201164de02824f  libstdc++-v3/.editorconfig
! 3b7b8dc985085961bd5ea2982a0223ca  libstdc++-v3/ChangeLog
  7aa6c40440a44fcf5ec94c066160c2f8  libstdc++-v3/ChangeLog-1998
  7aff86600b6a1ed3fa87305075a92db0  libstdc++-v3/ChangeLog-1999
  a6f28e8fc9bb07696a9e068b439a3a87  libstdc++-v3/ChangeLog-2000
*************** dc811926d3a0cc8410b37f38fd276e62  libstd
*** 134105,134111 ****
  7fdf3835a346e7ef9a3a8308d819b141  libstdc++-v3/testsuite/20_util/bind/cv_quals.cc
  3296aff77062491cdbb021ced8c9691a  libstdc++-v3/testsuite/20_util/bind/cv_quals_2.cc
  eb24581e6901c23d8bdbfca254833195  libstdc++-v3/testsuite/20_util/bind/cv_quals_3.cc
! 7108e4b81832823bce96a6c579a9a3c4  libstdc++-v3/testsuite/20_util/bind/dangling_ref.cc
  499a492e07678a83b4feca56bc7dec38  libstdc++-v3/testsuite/20_util/bind/is_placeholder_v.cc
  a8a56b45372ab9a92235b9c43274978f  libstdc++-v3/testsuite/20_util/bind/move.cc
  113518e192b41e33301c903e8048d393  libstdc++-v3/testsuite/20_util/bind/nested.cc
--- 134106,134112 ----
  7fdf3835a346e7ef9a3a8308d819b141  libstdc++-v3/testsuite/20_util/bind/cv_quals.cc
  3296aff77062491cdbb021ced8c9691a  libstdc++-v3/testsuite/20_util/bind/cv_quals_2.cc
  eb24581e6901c23d8bdbfca254833195  libstdc++-v3/testsuite/20_util/bind/cv_quals_3.cc
! 9e20c0553ba5c2a0e7032207ebaef1c2  libstdc++-v3/testsuite/20_util/bind/dangling_ref.cc
  499a492e07678a83b4feca56bc7dec38  libstdc++-v3/testsuite/20_util/bind/is_placeholder_v.cc
  a8a56b45372ab9a92235b9c43274978f  libstdc++-v3/testsuite/20_util/bind/move.cc
  113518e192b41e33301c903e8048d393  libstdc++-v3/testsuite/20_util/bind/nested.cc
*************** bdfa105b922bad5336a8c6d4533fc51f  libstd
*** 134941,134947 ****
  ff0ccdc05468ddce08d4ada91d33b781  libstdc++-v3/testsuite/20_util/ratio/operations/ops1.cc
  57f67e63ff4fb275bd9b09db383ca4df  libstdc++-v3/testsuite/20_util/ratio/operations/ops2.cc
  30cad9ff52b866b92a63310ead4f5c6c  libstdc++-v3/testsuite/20_util/ratio/operations/ops3.cc
! ad80681b6b901b11613ce8bef15006b3  libstdc++-v3/testsuite/20_util/ratio/operations/ops_overflow_neg.cc
  2397ab3807a9eb62ad653d874d58d857  libstdc++-v3/testsuite/20_util/ratio/requirements/constexpr_data.cc
  69afdb8700e22b161a1f973e70aff227  libstdc++-v3/testsuite/20_util/ratio/requirements/ratio_equal_v.cc
  d8bbe2c17046f08594a91f5a8e216ba7  libstdc++-v3/testsuite/20_util/ratio/requirements/type_constraints.cc
--- 134942,134948 ----
  ff0ccdc05468ddce08d4ada91d33b781  libstdc++-v3/testsuite/20_util/ratio/operations/ops1.cc
  57f67e63ff4fb275bd9b09db383ca4df  libstdc++-v3/testsuite/20_util/ratio/operations/ops2.cc
  30cad9ff52b866b92a63310ead4f5c6c  libstdc++-v3/testsuite/20_util/ratio/operations/ops3.cc
! a0585b8c8242c82e134c9055fdfd1dc9  libstdc++-v3/testsuite/20_util/ratio/operations/ops_overflow_neg.cc
  2397ab3807a9eb62ad653d874d58d857  libstdc++-v3/testsuite/20_util/ratio/requirements/constexpr_data.cc
  69afdb8700e22b161a1f973e70aff227  libstdc++-v3/testsuite/20_util/ratio/requirements/ratio_equal_v.cc
  d8bbe2c17046f08594a91f5a8e216ba7  libstdc++-v3/testsuite/20_util/ratio/requirements/type_constraints.cc
*************** e2b40f273adc9c3cdf931a505b25a3e3  libstd
*** 135404,135410 ****
  7cc86eac7379c689c0ac47faf59dee7f  libstdc++-v3/testsuite/20_util/unique_ptr/hash/types.cc
  865ecdda52bcc46067ae1155b4fc802d  libstdc++-v3/testsuite/20_util/unique_ptr/io/lwg2948.cc
  bb40414adb587ca6cdd1ffd17960c9e2  libstdc++-v3/testsuite/20_util/unique_ptr/lwg2762.cc
! a5234a3d63fc5d686aba74601e09973e  libstdc++-v3/testsuite/20_util/unique_ptr/lwg4148.cc
  a87ada64946cd931cadfaa13b513a900  libstdc++-v3/testsuite/20_util/unique_ptr/modifiers/43183.cc
  1dba41a3d994169c6dc80f6e218ba745  libstdc++-v3/testsuite/20_util/unique_ptr/modifiers/48398.cc
  1522af3c74e321802d64a0867e5e7e82  libstdc++-v3/testsuite/20_util/unique_ptr/modifiers/93562.cc
--- 135405,135411 ----
  7cc86eac7379c689c0ac47faf59dee7f  libstdc++-v3/testsuite/20_util/unique_ptr/hash/types.cc
  865ecdda52bcc46067ae1155b4fc802d  libstdc++-v3/testsuite/20_util/unique_ptr/io/lwg2948.cc
  bb40414adb587ca6cdd1ffd17960c9e2  libstdc++-v3/testsuite/20_util/unique_ptr/lwg2762.cc
! 455915dfcf4dc6251c24ac413d3dfcde  libstdc++-v3/testsuite/20_util/unique_ptr/lwg4148.cc
  a87ada64946cd931cadfaa13b513a900  libstdc++-v3/testsuite/20_util/unique_ptr/modifiers/43183.cc
  1dba41a3d994169c6dc80f6e218ba745  libstdc++-v3/testsuite/20_util/unique_ptr/modifiers/48398.cc
  1522af3c74e321802d64a0867e5e7e82  libstdc++-v3/testsuite/20_util/unique_ptr/modifiers/93562.cc
*************** c1f319ba7f6ad7a6795bac75046271d0  libstd
*** 141060,141066 ****
  6afaee620f593086673491093e9e2c83  libstdc++-v3/testsuite/29_atomics/atomic/operators/56011.cc
  e4b6fcfd2a515534e7ba19934850347b  libstdc++-v3/testsuite/29_atomics/atomic/operators/integral_assignment.cc
  23d004ef8bc7604cf4a60c8c4af4adc1  libstdc++-v3/testsuite/29_atomics/atomic/operators/integral_conversion.cc
! b3d8282607956ee4826df350c5a70605  libstdc++-v3/testsuite/29_atomics/atomic/operators/pointer_partial_void.cc
  68b6db9b9df1ee4ad267757efbd252a7  libstdc++-v3/testsuite/29_atomics/atomic/requirements/base_classes.cc
  4770655eced43833b45a7bff9815589f  libstdc++-v3/testsuite/29_atomics/atomic/requirements/compare_exchange_lowering.cc
  638a3151b6917b31577257fe25faead9  libstdc++-v3/testsuite/29_atomics/atomic/requirements/explicit_instantiation/1.cc
--- 141061,141067 ----
  6afaee620f593086673491093e9e2c83  libstdc++-v3/testsuite/29_atomics/atomic/operators/56011.cc
  e4b6fcfd2a515534e7ba19934850347b  libstdc++-v3/testsuite/29_atomics/atomic/operators/integral_assignment.cc
  23d004ef8bc7604cf4a60c8c4af4adc1  libstdc++-v3/testsuite/29_atomics/atomic/operators/integral_conversion.cc
! b085cfae753eed6df7ceab06181bf1de  libstdc++-v3/testsuite/29_atomics/atomic/operators/pointer_partial_void.cc
  68b6db9b9df1ee4ad267757efbd252a7  libstdc++-v3/testsuite/29_atomics/atomic/requirements/base_classes.cc
  4770655eced43833b45a7bff9815589f  libstdc++-v3/testsuite/29_atomics/atomic/requirements/compare_exchange_lowering.cc
  638a3151b6917b31577257fe25faead9  libstdc++-v3/testsuite/29_atomics/atomic/requirements/explicit_instantiation/1.cc
*************** ad9034013bdd2437cca11f0ba1ddc77e  libstd
*** 141267,141273 ****
  541a642f684120cf15e3efab97dbb1c6  libstdc++-v3/testsuite/30_threads/packaged_task/cons/alloc_min.cc
  f928b71e8e3379df3dec12c6778d93f9  libstdc++-v3/testsuite/30_threads/packaged_task/cons/assign_neg.cc
  0333461d9839e0cd5897823f742b9d34  libstdc++-v3/testsuite/30_threads/packaged_task/cons/copy_neg.cc
! ae44041381823a46a5ac2d066c71150e  libstdc++-v3/testsuite/30_threads/packaged_task/cons/dangling_ref.cc
  e3cd3b55ab1655176e9eae1b0b5f762e  libstdc++-v3/testsuite/30_threads/packaged_task/cons/deduction.cc
  ba4413ab6f8707eecf7439c419b333f6  libstdc++-v3/testsuite/30_threads/packaged_task/cons/deduction_c++23.cc
  a7699861951a48bd37d8f9e4d7d4d6ef  libstdc++-v3/testsuite/30_threads/packaged_task/cons/lwg4154_neg.cc
--- 141268,141274 ----
  541a642f684120cf15e3efab97dbb1c6  libstdc++-v3/testsuite/30_threads/packaged_task/cons/alloc_min.cc
  f928b71e8e3379df3dec12c6778d93f9  libstdc++-v3/testsuite/30_threads/packaged_task/cons/assign_neg.cc
  0333461d9839e0cd5897823f742b9d34  libstdc++-v3/testsuite/30_threads/packaged_task/cons/copy_neg.cc
! 1819879d3dc2788c98e2b8836daf3ddd  libstdc++-v3/testsuite/30_threads/packaged_task/cons/dangling_ref.cc
  e3cd3b55ab1655176e9eae1b0b5f762e  libstdc++-v3/testsuite/30_threads/packaged_task/cons/deduction.cc
  ba4413ab6f8707eecf7439c419b333f6  libstdc++-v3/testsuite/30_threads/packaged_task/cons/deduction_c++23.cc
  a7699861951a48bd37d8f9e4d7d4d6ef  libstdc++-v3/testsuite/30_threads/packaged_task/cons/lwg4154_neg.cc
diff -Nrcpad gcc-15-20250913/gcc/ChangeLog gcc-15-20250920/gcc/ChangeLog
*** gcc-15-20250913/gcc/ChangeLog	Sat Sep 13 22:32:05 2025
--- gcc-15-20250920/gcc/ChangeLog	Sat Sep 20 22:32:26 2025
***************
*** 1,3 ****
--- 1,75 ----
+ 2025-09-18  hongtao.liu  <hongtao.liu@intel.com>
+ 
+ 	Backported from master:
+ 	2025-09-18  hongtao.liu  <hongtao.liu@intel.com>
+ 
+ 	* config/i386/x86-tune.def (X86_TUNE_AVX512_MOVE_BY_PIECES):
+ 	Remove SPR/GNR/DMR.
+ 	(X86_TUNE_AVX512_STORE_BY_PIECES): Ditto.
+ 
+ 2025-09-16  Jeff Law  <jlaw@ventanamicro.com>
+ 
+ 	Backported from master:
+ 	2025-09-12  Jeff Law  <jlaw@ventanamicro.com>
+ 
+ 	* lra-constraints.cc (get_equiv): Bounds check before accessing
+ 	data in ira_reg_equiv.
+ 
+ 2025-09-16  Jennifer Schmitz  <jschmitz@nvidia.com>
+ 
+ 	PR target/121602
+ 	* config/aarch64/aarch64-sve-builtins.cc
+ 	(gimple_folder::fold_active_lanes_to): Add force_vector
+ 	statement.
+ 
+ 2025-09-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+ 
+ 	Backported from master:
+ 	2025-08-11  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+ 
+ 	PR target/121464
+ 	* config/arm/arm.md (arm_<mrrc>, arm_<mcrr>): Fix operand check.
+ 
+ 2025-09-15  Kyrylo Tkachov  <ktkachov@nvidia.com>
+ 
+ 	Backported from master:
+ 	2025-09-03  Kyrylo Tkachov  <ktkachov@nvidia.com>
+ 
+ 	PR target/121749
+ 	* config/aarch64/aarch64-simd.md (aarch64_<shrn_op>shrn_n<mode>):
+ 	Use aarch64_simd_shift_imm_offset_<vn_mode> instead of
+ 	aarch64_simd_shift_imm_offset_<ve_mode> predicate.
+ 	(aarch64_<shrn_op>shrn_n<mode> VQN define_expand): Likewise.
+ 	(*aarch64_<shrn_op>rshrn_n<mode>_insn): Likewise.
+ 	(aarch64_<shrn_op>rshrn_n<mode>): Likewise.
+ 	(aarch64_<shrn_op>rshrn_n<mode> VQN define_expand): Likewise.
+ 	(aarch64_sqshrun_n<mode>_insn): Likewise.
+ 	(aarch64_sqshrun_n<mode>): Likewise.
+ 	(aarch64_sqshrun_n<mode> VQN define_expand): Likewise.
+ 	(aarch64_sqrshrun_n<mode>_insn): Likewise.
+ 	(aarch64_sqrshrun_n<mode>): Likewise.
+ 	(aarch64_sqrshrun_n<mode>): Likewise.
+ 	* config/aarch64/iterators.md (vn_mode): Handle DI, SI, HI modes.
+ 
+ 2025-09-15  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	Backported from master:
+ 	2025-09-15  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	* config/avr/avr-mcus.def: Add avr32eb14, avr32eb20,
+ 	avr32eb28, avr32eb32.
+ 	* doc/avr-mmcu.texi: Rebuild.
+ 
+ 2025-09-15  Xi Ruoyao  <xry111@xry111.site>
+ 
+ 	Backported from master:
+ 	2025-09-15  Xi Ruoyao  <xry111@xry111.site>
+ 
+ 	PR target/121906
+ 	* config/loongarch/loongarch.md (*bstrins_<mode>_for_ior_mask):
+ 	Always create a new pseudo for the input register of the bstrins
+ 	instruction.
+ 
  2025-09-11  Richard Sandiford  <rdsandiford@googlemail.com>
  
  	PR rtl-optimization/121757
diff -Nrcpad gcc-15-20250913/gcc/DATESTAMP gcc-15-20250920/gcc/DATESTAMP
*** gcc-15-20250913/gcc/DATESTAMP	Sat Sep 13 22:32:05 2025
--- gcc-15-20250920/gcc/DATESTAMP	Sat Sep 20 22:32:27 2025
***************
*** 1 ****
! 20250913
--- 1 ----
! 20250920
diff -Nrcpad gcc-15-20250913/gcc/ada/ChangeLog gcc-15-20250920/gcc/ada/ChangeLog
*** gcc-15-20250913/gcc/ada/ChangeLog	Sat Sep 13 22:32:05 2025
--- gcc-15-20250920/gcc/ada/ChangeLog	Sat Sep 20 22:32:27 2025
***************
*** 1,3 ****
--- 1,25 ----
+ 2025-09-15  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	* gcc-interface/trans.cc (gnat_to_gnu)
+ 	<N_Object_Renaming_Declaration>: Deal with objects whose elaboration
+ 	is deferred.
+ 	(process_freeze_entity): Deal with renamed objects whose elaboration
+ 	is deferred.
+ 
+ 2025-09-15  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	* checks.adb (Apply_Discriminant_Check): Remove undocumented test
+ 	on Is_Aliased_View applied to the left-hand side to skip the check
+ 	in the case where the subtypes are the same, and replace it with a
+ 	test that the subtypes are constrained.
+ 
+ 2025-09-15  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	* exp_util.adb (Finalize_Address): In an untagged derivation, call
+ 	Root_Type on the full view of the base type if the partial view is
+ 	itself not a derived type.
+ 	(Is_Untagged_Derivation): Minor formatting tweak.
+ 
  2025-09-11  Gary Dismukes  <dismukes@adacore.com>
  
  	* exp_aggr.adb (Build_Container_Aggr_Code.Build_Size_Expr): In the case
diff -Nrcpad gcc-15-20250913/gcc/ada/checks.adb gcc-15-20250920/gcc/ada/checks.adb
*** gcc-15-20250913/gcc/ada/checks.adb	Sat Sep 13 22:32:05 2025
--- gcc-15-20250920/gcc/ada/checks.adb	Sat Sep 20 22:32:27 2025
*************** package body Checks is
*** 1539,1559 ****
           return;
        end if;
  
!       --  Suppress checks if the subtypes are the same. The check must be
!       --  preserved in an assignment to a formal, because the constraint is
!       --  given by the actual.
  
        if Nkind (Original_Node (N)) /= N_Allocator
          and then (No (Lhs)
                     or else not Is_Entity_Name (Lhs)
                     or else No (Param_Entity (Lhs)))
        then
!          if (Etype (N) = Typ
!               or else (Do_Access and then Designated_Type (Typ) = S_Typ))
!            and then (No (Lhs) or else not Is_Aliased_View (Lhs))
!          then
!             return;
!          end if;
  
        --  We can also eliminate checks on allocators with a subtype mark that
        --  coincides with the context type. The context type may be a subtype
--- 1539,1556 ----
           return;
        end if;
  
!       --  Suppress checks if the subtypes are the same and constrained. The
!       --  check must be preserved in an assignment to a formal, because the
!       --  constraint is given by the actual.
  
        if Nkind (Original_Node (N)) /= N_Allocator
+         and then (if Do_Access then Designated_Type (Typ) else Typ) = S_Typ
+         and then Is_Constrained (S_Typ)
          and then (No (Lhs)
                     or else not Is_Entity_Name (Lhs)
                     or else No (Param_Entity (Lhs)))
        then
!          return;
  
        --  We can also eliminate checks on allocators with a subtype mark that
        --  coincides with the context type. The context type may be a subtype
diff -Nrcpad gcc-15-20250913/gcc/ada/exp_util.adb gcc-15-20250920/gcc/ada/exp_util.adb
*** gcc-15-20250913/gcc/ada/exp_util.adb	Sat Sep 13 22:32:05 2025
--- gcc-15-20250920/gcc/ada/exp_util.adb	Sat Sep 20 22:32:27 2025
*************** package body Exp_Util is
*** 6080,6086 ****
              Utyp := Corresponding_Record_Type (Root_Type (Btyp));
  
           elsif Is_Implicit_Full_View (Utyp) then
!             Utyp := Underlying_Type (Root_Type (Btyp));
  
              if Is_Protected_Type (Utyp) then
                 Utyp := Corresponding_Record_Type (Utyp);
--- 6080,6090 ----
              Utyp := Corresponding_Record_Type (Root_Type (Btyp));
  
           elsif Is_Implicit_Full_View (Utyp) then
!             if Is_Derived_Type (Btyp) then
!                Utyp := Underlying_Type (Root_Type (Btyp));
!             else
!                Utyp := Underlying_Type (Root_Type (Full_View (Btyp)));
!             end if;
  
              if Is_Protected_Type (Utyp) then
                 Utyp := Corresponding_Record_Type (Utyp);
*************** package body Exp_Util is
*** 9907,9913 ****
     begin
        return (not Is_Tagged_Type (T) and then Is_Derived_Type (T))
                 or else
!                  (Is_Private_Type (T) and then Present (Full_View (T))
                     and then not Is_Tagged_Type (Full_View (T))
                     and then Is_Derived_Type (Full_View (T))
                     and then Etype (Full_View (T)) /= T);
--- 9911,9918 ----
     begin
        return (not Is_Tagged_Type (T) and then Is_Derived_Type (T))
                 or else
!                  (Is_Private_Type (T)
!                    and then Present (Full_View (T))
                     and then not Is_Tagged_Type (Full_View (T))
                     and then Is_Derived_Type (Full_View (T))
                     and then Etype (Full_View (T)) /= T);
diff -Nrcpad gcc-15-20250913/gcc/ada/gcc-interface/trans.cc gcc-15-20250920/gcc/ada/gcc-interface/trans.cc
*** gcc-15-20250913/gcc/ada/gcc-interface/trans.cc	Sat Sep 13 22:32:05 2025
--- gcc-15-20250920/gcc/ada/gcc-interface/trans.cc	Sat Sep 20 22:32:27 2025
*************** gnat_to_gnu (Node_Id gnat_node)
*** 6855,6863 ****
  		&& (Is_Array_Type (Etype (gnat_temp))
  		    || Is_Record_Type (Etype (gnat_temp))
  		    || Is_Concurrent_Type (Etype (gnat_temp)))))
! 	gnat_to_gnu_entity (gnat_temp,
! 			    gnat_to_gnu (Renamed_Object (gnat_temp)),
! 			    true);
        break;
  
      case N_Exception_Renaming_Declaration:
--- 6855,6876 ----
  		&& (Is_Array_Type (Etype (gnat_temp))
  		    || Is_Record_Type (Etype (gnat_temp))
  		    || Is_Concurrent_Type (Etype (gnat_temp)))))
! 	{
! 	  gnu_expr = gnat_to_gnu (Renamed_Object (gnat_temp));
! 
! 	  /* The elaboration of object renamings present in the source code
! 	     never needs to be deferred.  But regular objects may be turned
! 	     into renamings during expansion and their elaboration may need
! 	     to be deferred, in which case we expect the renamed references
! 	     to have been stabilized, so we do not do it again here.  */
! 	  if (Present (Freeze_Node (gnat_temp)))
! 	    {
! 	      gcc_assert (!Comes_From_Source (gnat_node));
! 	      save_gnu_tree (gnat_node, gnu_expr, true);
! 	    }
! 	  else
! 	    gnat_to_gnu_entity (gnat_temp, gnu_expr, true);
! 	}
        break;
  
      case N_Exception_Renaming_Declaration:
*************** process_freeze_entity (Node_Id gnat_node
*** 9775,9784 ****
      }
    else
      {
        tree gnu_init
! 	= (Nkind (Declaration_Node (gnat_entity)) == N_Object_Declaration
! 	   && present_gnu_tree (Declaration_Node (gnat_entity)))
! 	  ? get_gnu_tree (Declaration_Node (gnat_entity)) : NULL_TREE;
  
        gnu_new = gnat_to_gnu_entity (gnat_entity, gnu_init, true);
      }
--- 9788,9802 ----
      }
    else
      {
+       /* For an object whose elaboration is deferred, the GCC tree of the
+ 	 declaration, if any, is the initialization expression.  */
+       const Node_Id gnat_decl = Declaration_Node (gnat_entity);
        tree gnu_init
! 	= (Nkind (gnat_decl) == N_Object_Declaration
! 	   || Nkind (gnat_decl) == N_Object_Renaming_Declaration)
! 	  && Present (Freeze_Node (gnat_entity))
! 	  && present_gnu_tree (gnat_decl)
! 	  ? get_gnu_tree (gnat_decl) : NULL_TREE;
  
        gnu_new = gnat_to_gnu_entity (gnat_entity, gnu_init, true);
      }
diff -Nrcpad gcc-15-20250913/gcc/config/aarch64/aarch64-simd.md gcc-15-20250920/gcc/config/aarch64/aarch64-simd.md
*** gcc-15-20250913/gcc/config/aarch64/aarch64-simd.md	Sat Sep 13 22:32:06 2025
--- gcc-15-20250920/gcc/config/aarch64/aarch64-simd.md	Sat Sep 20 22:32:28 2025
***************
*** 6678,6684 ****
  	(SAT_TRUNC:<VNARROWQ>
  	  (<TRUNC_SHIFT>:SD_HSDI
  	    (match_operand:SD_HSDI 1 "register_operand" "w")
! 	    (match_operand:SI 2 "aarch64_simd_shift_imm_offset_<ve_mode>"))))]
    "TARGET_SIMD"
    "<shrn_op>shrn\t%<vn2>0<Vmntype>, %<v>1<Vmtype>, %2"
    [(set_attr "type" "neon_shift_imm_narrow_q")]
--- 6678,6684 ----
  	(SAT_TRUNC:<VNARROWQ>
  	  (<TRUNC_SHIFT>:SD_HSDI
  	    (match_operand:SD_HSDI 1 "register_operand" "w")
! 	    (match_operand:SI 2 "aarch64_simd_shift_imm_offset_<vn_mode>"))))]
    "TARGET_SIMD"
    "<shrn_op>shrn\t%<vn2>0<Vmntype>, %<v>1<Vmtype>, %2"
    [(set_attr "type" "neon_shift_imm_narrow_q")]
***************
*** 6700,6706 ****
  	(ALL_TRUNC:<VNARROWQ>
  	  (<TRUNC_SHIFT>:VQN
  	    (match_operand:VQN 1 "register_operand")
! 	    (match_operand:SI 2 "aarch64_simd_shift_imm_offset_<ve_mode>"))))]
    "TARGET_SIMD"
    {
      operands[2] = aarch64_simd_gen_const_vector_dup (<MODE>mode,
--- 6700,6706 ----
  	(ALL_TRUNC:<VNARROWQ>
  	  (<TRUNC_SHIFT>:VQN
  	    (match_operand:VQN 1 "register_operand")
! 	    (match_operand:SI 2 "aarch64_simd_shift_imm_offset_<vn_mode>"))))]
    "TARGET_SIMD"
    {
      operands[2] = aarch64_simd_gen_const_vector_dup (<MODE>mode,
***************
*** 6731,6737 ****
  	      (<TRUNCEXTEND>:<DWI>
  	        (match_operand:SD_HSDI 1 "register_operand" "w"))
  	      (match_operand:<DWI> 3 "aarch64_int_rnd_operand"))
! 	    (match_operand:SI 2 "aarch64_simd_shift_imm_offset_<ve_mode>"))))]
    "TARGET_SIMD
     && aarch64_const_vec_rnd_cst_p (operands[3], operands[2])"
    "<shrn_op>rshrn\t%<vn2>0<Vmntype>, %<v>1<Vmtype>, %2"
--- 6731,6737 ----
  	      (<TRUNCEXTEND>:<DWI>
  	        (match_operand:SD_HSDI 1 "register_operand" "w"))
  	      (match_operand:<DWI> 3 "aarch64_int_rnd_operand"))
! 	    (match_operand:SI 2 "aarch64_simd_shift_imm_offset_<vn_mode>"))))]
    "TARGET_SIMD
     && aarch64_const_vec_rnd_cst_p (operands[3], operands[2])"
    "<shrn_op>rshrn\t%<vn2>0<Vmntype>, %<v>1<Vmtype>, %2"
***************
*** 6746,6752 ****
  	      (<TRUNCEXTEND>:<V2XWIDE>
  	        (match_operand:SD_HSDI 1 "register_operand"))
  	      (match_dup 3))
! 	    (match_operand:SI 2 "aarch64_simd_shift_imm_offset_<ve_mode>"))))]
    "TARGET_SIMD"
    {
      /* Use this expander to create the rounding constant vector, which is
--- 6746,6752 ----
  	      (<TRUNCEXTEND>:<V2XWIDE>
  	        (match_operand:SD_HSDI 1 "register_operand"))
  	      (match_dup 3))
! 	    (match_operand:SI 2 "aarch64_simd_shift_imm_offset_<vn_mode>"))))]
    "TARGET_SIMD"
    {
      /* Use this expander to create the rounding constant vector, which is
***************
*** 6766,6772 ****
  	      (<TRUNCEXTEND>:<V2XWIDE>
  	        (match_operand:VQN 1 "register_operand"))
  	      (match_dup 3))
! 	    (match_operand:SI 2 "aarch64_simd_shift_imm_offset_<ve_mode>"))))]
    "TARGET_SIMD"
    {
      if (<CODE> == TRUNCATE
--- 6766,6772 ----
  	      (<TRUNCEXTEND>:<V2XWIDE>
  	        (match_operand:VQN 1 "register_operand"))
  	      (match_dup 3))
! 	    (match_operand:SI 2 "aarch64_simd_shift_imm_offset_<vn_mode>"))))]
    "TARGET_SIMD"
    {
      if (<CODE> == TRUNCATE
***************
*** 6808,6814 ****
  	  (smax:SD_HSDI
  	    (ashiftrt:SD_HSDI
  	      (match_operand:SD_HSDI 1 "register_operand" "w")
! 	      (match_operand:SI 2 "aarch64_simd_shift_imm_offset_<ve_mode>"))
  	    (const_int 0))
  	  (const_int <half_mask>)))]
    "TARGET_SIMD"
--- 6808,6814 ----
  	  (smax:SD_HSDI
  	    (ashiftrt:SD_HSDI
  	      (match_operand:SD_HSDI 1 "register_operand" "w")
! 	      (match_operand:SI 2 "aarch64_simd_shift_imm_offset_<vn_mode>"))
  	    (const_int 0))
  	  (const_int <half_mask>)))]
    "TARGET_SIMD"
***************
*** 6819,6825 ****
  (define_expand "aarch64_sqshrun_n<mode>"
    [(match_operand:<VNARROWQ> 0 "register_operand")
     (match_operand:SD_HSDI 1 "register_operand")
!    (match_operand:SI 2 "aarch64_simd_shift_imm_offset_<ve_mode>")]
    "TARGET_SIMD"
    {
      rtx dst = gen_reg_rtx (<MODE>mode);
--- 6819,6825 ----
  (define_expand "aarch64_sqshrun_n<mode>"
    [(match_operand:<VNARROWQ> 0 "register_operand")
     (match_operand:SD_HSDI 1 "register_operand")
!    (match_operand:SI 2 "aarch64_simd_shift_imm_offset_<vn_mode>")]
    "TARGET_SIMD"
    {
      rtx dst = gen_reg_rtx (<MODE>mode);
***************
*** 6837,6843 ****
  	    (smax:VQN
  	      (ashiftrt:VQN
  		(match_operand:VQN 1 "register_operand")
! 		(match_operand:SI 2 "aarch64_simd_shift_imm_offset_<ve_mode>"))
  	      (match_dup 3))
  	    (match_dup 4))))]
    "TARGET_SIMD"
--- 6837,6843 ----
  	    (smax:VQN
  	      (ashiftrt:VQN
  		(match_operand:VQN 1 "register_operand")
! 		(match_operand:SI 2 "aarch64_simd_shift_imm_offset_<vn_mode>"))
  	      (match_dup 3))
  	    (match_dup 4))))]
    "TARGET_SIMD"
***************
*** 6879,6885 ****
  		(sign_extend:<DWI>
  		  (match_operand:SD_HSDI 1 "register_operand" "w"))
  		(match_operand:<DWI> 3 "aarch64_int_rnd_operand"))
! 	      (match_operand:SI 2 "aarch64_simd_shift_imm_offset_<ve_mode>"))
  	    (const_int 0))
  	  (const_int <half_mask>)))]
    "TARGET_SIMD
--- 6879,6885 ----
  		(sign_extend:<DWI>
  		  (match_operand:SD_HSDI 1 "register_operand" "w"))
  		(match_operand:<DWI> 3 "aarch64_int_rnd_operand"))
! 	      (match_operand:SI 2 "aarch64_simd_shift_imm_offset_<vn_mode>"))
  	    (const_int 0))
  	  (const_int <half_mask>)))]
    "TARGET_SIMD
***************
*** 6891,6897 ****
  (define_expand "aarch64_sqrshrun_n<mode>"
    [(match_operand:<VNARROWQ> 0 "register_operand")
     (match_operand:SD_HSDI 1 "register_operand")
!    (match_operand:SI 2 "aarch64_simd_shift_imm_offset_<ve_mode>")]
    "TARGET_SIMD"
    {
      int prec = GET_MODE_UNIT_PRECISION (<DWI>mode);
--- 6891,6897 ----
  (define_expand "aarch64_sqrshrun_n<mode>"
    [(match_operand:<VNARROWQ> 0 "register_operand")
     (match_operand:SD_HSDI 1 "register_operand")
!    (match_operand:SI 2 "aarch64_simd_shift_imm_offset_<vn_mode>")]
    "TARGET_SIMD"
    {
      int prec = GET_MODE_UNIT_PRECISION (<DWI>mode);
***************
*** 6914,6920 ****
  		  (sign_extend:<V2XWIDE>
  		    (match_operand:VQN 1 "register_operand"))
  		  (match_dup 3))
! 		(match_operand:SI 2 "aarch64_simd_shift_imm_offset_<ve_mode>"))
  	      (match_dup 4))
  	    (match_dup 5))))]
    "TARGET_SIMD"
--- 6914,6920 ----
  		  (sign_extend:<V2XWIDE>
  		    (match_operand:VQN 1 "register_operand"))
  		  (match_dup 3))
! 		(match_operand:SI 2 "aarch64_simd_shift_imm_offset_<vn_mode>"))
  	      (match_dup 4))
  	    (match_dup 5))))]
    "TARGET_SIMD"
diff -Nrcpad gcc-15-20250913/gcc/config/aarch64/aarch64-sve-builtins.cc gcc-15-20250920/gcc/config/aarch64/aarch64-sve-builtins.cc
*** gcc-15-20250913/gcc/config/aarch64/aarch64-sve-builtins.cc	Sat Sep 13 22:32:06 2025
--- gcc-15-20250920/gcc/config/aarch64/aarch64-sve-builtins.cc	Sat Sep 20 22:32:28 2025
*************** gimple_folder::fold_active_lanes_to (tre
*** 3799,3804 ****
--- 3799,3805 ----
  
    gimple_seq stmts = NULL;
    tree pred = convert_pred (stmts, vector_type (0), 0);
+   x = force_vector (stmts, TREE_TYPE (lhs), x);
    gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
    return gimple_build_assign (lhs, VEC_COND_EXPR, pred, x, vec_inactive);
  }
diff -Nrcpad gcc-15-20250913/gcc/config/aarch64/iterators.md gcc-15-20250920/gcc/config/aarch64/iterators.md
*** gcc-15-20250913/gcc/config/aarch64/iterators.md	Sat Sep 13 22:32:06 2025
--- gcc-15-20250920/gcc/config/aarch64/iterators.md	Sat Sep 20 22:32:28 2025
***************
*** 2126,2132 ****
  			   (SI   "si")])
  
  ;; Like ve_mode but for the half-width modes.
! (define_mode_attr vn_mode [(V8HI  "qi") (V4SI  "hi") (V2DI  "si")])
  
  ;; Vm for lane instructions is restricted to FP_LO_REGS.
  (define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x")
--- 2126,2133 ----
  			   (SI   "si")])
  
  ;; Like ve_mode but for the half-width modes.
! (define_mode_attr vn_mode [(V8HI  "qi") (V4SI  "hi") (V2DI  "si") (DI "si")
! 			   (SI "hi") (HI "qi")])
  
  ;; Vm for lane instructions is restricted to FP_LO_REGS.
  (define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x")
diff -Nrcpad gcc-15-20250913/gcc/config/arm/arm.md gcc-15-20250920/gcc/config/arm/arm.md
*** gcc-15-20250913/gcc/config/arm/arm.md	Sat Sep 13 22:32:06 2025
--- gcc-15-20250920/gcc/config/arm/arm.md	Sat Sep 20 22:32:28 2025
***************
*** 13044,13050 ****
    "arm_coproc_builtin_available (VUNSPEC_<MCRR>)"
  {
    arm_const_bounds (operands[0], 0, 16);
!   arm_const_bounds (operands[1], 0, 8);
    arm_const_bounds (operands[3], 0, (1 << 5));
    return "<mcrr>\\tp%c0, %1, %Q2, %R2, CR%c3";
  }
--- 13044,13050 ----
    "arm_coproc_builtin_available (VUNSPEC_<MCRR>)"
  {
    arm_const_bounds (operands[0], 0, 16);
!   arm_const_bounds (operands[1], 0, 16);
    arm_const_bounds (operands[3], 0, (1 << 5));
    return "<mcrr>\\tp%c0, %1, %Q2, %R2, CR%c3";
  }
***************
*** 13059,13065 ****
    "arm_coproc_builtin_available (VUNSPEC_<MRRC>)"
  {
    arm_const_bounds (operands[1], 0, 16);
!   arm_const_bounds (operands[2], 0, 8);
    arm_const_bounds (operands[3], 0, (1 << 5));
    return "<mrrc>\\tp%c1, %2, %Q0, %R0, CR%c3";
  }
--- 13059,13065 ----
    "arm_coproc_builtin_available (VUNSPEC_<MRRC>)"
  {
    arm_const_bounds (operands[1], 0, 16);
!   arm_const_bounds (operands[2], 0, 16);
    arm_const_bounds (operands[3], 0, (1 << 5));
    return "<mrrc>\\tp%c1, %2, %Q0, %R0, CR%c3";
  }
diff -Nrcpad gcc-15-20250913/gcc/config/avr/avr-mcus.def gcc-15-20250920/gcc/config/avr/avr-mcus.def
*** gcc-15-20250913/gcc/config/avr/avr-mcus.def	Sat Sep 13 22:32:06 2025
--- gcc-15-20250920/gcc/config/avr/avr-mcus.def	Sat Sep 20 22:32:28 2025
*************** AVR_MCU ("avr16eb14",        ARCH_AVRXME
*** 411,416 ****
--- 411,420 ----
  AVR_MCU ("avr16eb20",        ARCH_AVRXMEGA3, AVR_CVT,                 "__AVR_AVR16EB20__",   0x7800, 0x0, 0x4000, 0x8000)
  AVR_MCU ("avr16eb28",        ARCH_AVRXMEGA3, AVR_CVT,                 "__AVR_AVR16EB28__",   0x7800, 0x0, 0x4000, 0x8000)
  AVR_MCU ("avr16eb32",        ARCH_AVRXMEGA3, AVR_CVT,                 "__AVR_AVR16EB32__",   0x7800, 0x0, 0x4000, 0x8000)
+ AVR_MCU ("avr32eb14",        ARCH_AVRXMEGA3, AVR_CVT,                 "__AVR_AVR32EB14__",   0x7400, 0x0, 0x8000, 0x8000)
+ AVR_MCU ("avr32eb20",        ARCH_AVRXMEGA3, AVR_CVT,                 "__AVR_AVR32EB20__",   0x7400, 0x0, 0x8000, 0x8000)
+ AVR_MCU ("avr32eb28",        ARCH_AVRXMEGA3, AVR_CVT,                 "__AVR_AVR32EB28__",   0x7400, 0x0, 0x8000, 0x8000)
+ AVR_MCU ("avr32eb32",        ARCH_AVRXMEGA3, AVR_CVT,                 "__AVR_AVR32EB32__",   0x7400, 0x0, 0x8000, 0x8000)
  AVR_MCU ("avr16ea28",        ARCH_AVRXMEGA3, AVR_CVT,                 "__AVR_AVR16EA28__",   0x7800, 0x0, 0x4000, 0x8000)
  AVR_MCU ("avr16ea32",        ARCH_AVRXMEGA3, AVR_CVT,                 "__AVR_AVR16EA32__",   0x7800, 0x0, 0x4000, 0x8000)
  AVR_MCU ("avr16ea48",        ARCH_AVRXMEGA3, AVR_CVT,                 "__AVR_AVR16EA48__",   0x7800, 0x0, 0x4000, 0x8000)
diff -Nrcpad gcc-15-20250913/gcc/config/i386/x86-tune.def gcc-15-20250920/gcc/config/i386/x86-tune.def
*** gcc-15-20250913/gcc/config/i386/x86-tune.def	Sat Sep 13 22:32:06 2025
--- gcc-15-20250920/gcc/config/i386/x86-tune.def	Sat Sep 20 22:32:28 2025
*************** DEF_TUNE (X86_TUNE_AVX256_AVOID_VEC_PERM
*** 607,612 ****
--- 607,614 ----
  /* X86_TUNE_AVX256_SPLIT_REGS: if true, AVX512 ops are split into two AVX256 ops.  */
  DEF_TUNE (X86_TUNE_AVX512_SPLIT_REGS, "avx512_split_regs", m_ZNVER4)
  
+ /* It's better to align MOVE_MAX with prefer_vector_width to reduce
+    risk of STLF stalls(small store followed by big load.)  */
  /* X86_TUNE_AVX256_MOVE_BY_PIECES: Optimize move_by_pieces with 256-bit
     AVX instructions.  */
  DEF_TUNE (X86_TUNE_AVX256_MOVE_BY_PIECES, "avx256_move_by_pieces",
*************** DEF_TUNE (X86_TUNE_AVX256_STORE_BY_PIECE
*** 620,633 ****
  /* X86_TUNE_AVX512_MOVE_BY_PIECES: Optimize move_by_pieces with 512-bit
     AVX instructions.  */
  DEF_TUNE (X86_TUNE_AVX512_MOVE_BY_PIECES, "avx512_move_by_pieces",
! 	  m_SAPPHIRERAPIDS | m_GRANITERAPIDS | m_GRANITERAPIDS_D
! 	  | m_DIAMONDRAPIDS | m_ZNVER4 | m_ZNVER5)
  
  /* X86_TUNE_AVX512_STORE_BY_PIECES: Optimize store_by_pieces with 512-bit
     AVX instructions.  */
  DEF_TUNE (X86_TUNE_AVX512_STORE_BY_PIECES, "avx512_store_by_pieces",
! 	  m_SAPPHIRERAPIDS | m_GRANITERAPIDS | m_GRANITERAPIDS_D
! 	  | m_DIAMONDRAPIDS | m_ZNVER4 | m_ZNVER5)
  
  /* X86_TUNE_AVX512_TWO_EPILOGUES: Use two vector epilogues for 512-bit
     vectorized loops.  */
--- 622,633 ----
  /* X86_TUNE_AVX512_MOVE_BY_PIECES: Optimize move_by_pieces with 512-bit
     AVX instructions.  */
  DEF_TUNE (X86_TUNE_AVX512_MOVE_BY_PIECES, "avx512_move_by_pieces",
! 	   m_ZNVER4 | m_ZNVER5)
  
  /* X86_TUNE_AVX512_STORE_BY_PIECES: Optimize store_by_pieces with 512-bit
     AVX instructions.  */
  DEF_TUNE (X86_TUNE_AVX512_STORE_BY_PIECES, "avx512_store_by_pieces",
! 	  m_ZNVER4 | m_ZNVER5)
  
  /* X86_TUNE_AVX512_TWO_EPILOGUES: Use two vector epilogues for 512-bit
     vectorized loops.  */
diff -Nrcpad gcc-15-20250913/gcc/config/loongarch/loongarch.md gcc-15-20250920/gcc/config/loongarch/loongarch.md
*** gcc-15-20250913/gcc/config/loongarch/loongarch.md	Sat Sep 13 22:32:06 2025
--- gcc-15-20250920/gcc/config/loongarch/loongarch.md	Sat Sep 20 22:32:28 2025
***************
*** 1619,1631 ****
      operands[2] = GEN_INT (len);
      operands[4] = GEN_INT (lo);
  
!     if (lo)
!       {
! 	rtx tmp = gen_reg_rtx (<MODE>mode);
! 	emit_move_insn (tmp, gen_rtx_ASHIFTRT(<MODE>mode, operands[3],
! 					      GEN_INT (lo)));
! 	operands[3] = tmp;
!       }
    })
  
  ;; We always avoid the shift operation in bstrins_<mode>_for_ior_mask
--- 1619,1631 ----
      operands[2] = GEN_INT (len);
      operands[4] = GEN_INT (lo);
  
!     /* Use a new pseudo register even if lo == 0 or we'll wreck havoc
!        when operands[0] is same as operands[3].  See PR 121906.  */
!     rtx tmp = gen_reg_rtx (<MODE>mode);
!     rtx val = lo ? gen_rtx_ASHIFTRT (<MODE>mode, operands[3], GEN_INT (lo))
! 		 : operands[3];
!     emit_move_insn (tmp, val);
!     operands[3] = tmp;
    })
  
  ;; We always avoid the shift operation in bstrins_<mode>_for_ior_mask
diff -Nrcpad gcc-15-20250913/gcc/config/microblaze/iterators.md gcc-15-20250920/gcc/config/microblaze/iterators.md
*** gcc-15-20250913/gcc/config/microblaze/iterators.md	Thu Jan  1 00:00:00 1970
--- gcc-15-20250920/gcc/config/microblaze/iterators.md	Sat Sep 20 22:32:28 2025
***************
*** 0 ****
--- 1,25 ----
+ ;; Iterator definitions for GCC MicroBlaze machine description files.
+ ;; Copyright (C) 2012-2024 Free Software Foundation, Inc.
+ ;;
+ ;; This file is part of GCC.
+ ;;
+ ;; GCC is free software; you can redistribute it and/or modify
+ ;; it under the terms of the GNU General Public License as published by
+ ;; the Free Software Foundation; either version 3, or (at your option)
+ ;; any later version.
+ ;;
+ ;; GCC is distributed in the hope that it will be useful,
+ ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+ ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ ;; GNU General Public License for more details.
+ ;;
+ ;; You should have received a copy of the GNU General Public License
+ ;; along with GCC; see the file COPYING3.  If not see
+ ;; <http://www.gnu.org/licenses/>.
+ 
+ ; atomics code iterator
+ (define_code_iterator any_atomic [plus ior xor and])
+ 
+ ; atomics code attribute
+ (define_code_attr atomic_optab
+   [(plus "add") (ior "or") (xor "xor") (and "and")])
diff -Nrcpad gcc-15-20250913/gcc/config/microblaze/microblaze-protos.h gcc-15-20250920/gcc/config/microblaze/microblaze-protos.h
*** gcc-15-20250913/gcc/config/microblaze/microblaze-protos.h	Sat Sep 13 22:32:06 2025
--- gcc-15-20250920/gcc/config/microblaze/microblaze-protos.h	Sat Sep 20 22:32:28 2025
*************** extern int symbol_mentioned_p (rtx);
*** 62,67 ****
--- 62,68 ----
  extern int label_mentioned_p (rtx);
  extern bool microblaze_cannot_force_const_mem (machine_mode, rtx);
  extern void microblaze_eh_return (rtx op0);
+ extern void microblaze_subword_address (rtx, rtx *, rtx *);
  #endif  /* RTX_CODE */
  
  /* Declare functions in microblaze-c.cc.  */
diff -Nrcpad gcc-15-20250913/gcc/config/microblaze/microblaze.cc gcc-15-20250920/gcc/config/microblaze/microblaze.cc
*** gcc-15-20250913/gcc/config/microblaze/microblaze.cc	Sat Sep 13 22:32:06 2025
--- gcc-15-20250920/gcc/config/microblaze/microblaze.cc	Sat Sep 20 22:32:28 2025
*************** microblaze_expand_block_move (rtx dest,
*** 1300,1305 ****
--- 1300,1333 ----
    return false;
  }
  
+ /* Compute memory address *aligned_mem and corresponding shift value (*shift)
+    from a QImode memory reference MEM */
+ void
+ microblaze_subword_address (rtx mem, rtx *aligned_mem, rtx *shift)
+ {
+   /* Align the memory address to a word.  */
+   rtx addr = force_reg (Pmode, XEXP (mem, 0));
+ 
+   rtx addr_mask = gen_int_mode (-4, Pmode);
+ 
+   rtx aligned_addr = gen_reg_rtx (Pmode);
+ 
+   emit_move_insn (aligned_addr,  gen_rtx_AND (Pmode, addr, addr_mask));
+ 
+   *aligned_mem = change_address (mem, SImode, aligned_addr);
+ 
+   /* Calculate the shift amount.  */
+   emit_move_insn (*shift, gen_rtx_AND (SImode, addr, gen_int_mode (3, SImode)));
+ 
+   if (TARGET_LITTLE_ENDIAN == 0) {
+     emit_move_insn (*shift,
+ 		    gen_rtx_MINUS (SImode, gen_int_mode (3, SImode), *shift));
+   }
+ 
+   emit_move_insn (*shift, gen_rtx_ASHIFT (SImode, *shift,
+ 					  gen_int_mode (3, SImode)));
+ }
+ 
  static bool
  microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED,
  		      int opno ATTRIBUTE_UNUSED, int *total,
diff -Nrcpad gcc-15-20250913/gcc/config/microblaze/microblaze.md gcc-15-20250920/gcc/config/microblaze/microblaze.md
*** gcc-15-20250913/gcc/config/microblaze/microblaze.md	Sat Sep 13 22:32:06 2025
--- gcc-15-20250920/gcc/config/microblaze/microblaze.md	Sat Sep 20 22:32:28 2025
***************
*** 21,26 ****
--- 21,27 ----
  
  (include "constraints.md")
  (include "predicates.md")
+ (include "iterators.md")
  
  ;;----------------------------------------------------
  ;; Constants
***************
*** 43,48 ****
--- 44,53 ----
    (UNSPEC_TLS           106)    ;; jump table
    (UNSPEC_SET_TEXT      107)    ;; set text start
    (UNSPEC_TEXT          108)    ;; data text relative
+   (UNSPECV_CAS_BOOL     201)    ;; compare and swap (bool)
+   (UNSPECV_CAS_VAL      202)    ;; compare and swap (val)
+   (UNSPECV_CAS_MEM      203)    ;; compare and swap (mem)
+   (UNSPECV_ATOMIC_FETCH_OP     204)    ;; atomic fetch op
  ])
  
  (define_c_enum "unspec" [
***************
*** 79,85 ****
  ;; bshift 	Shift operations
  
  (define_attr "type"
!   "unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt,trap"
    (const_string "unknown"))
  
  ;; Main data type used by the insn
--- 84,90 ----
  ;; bshift 	Shift operations
  
  (define_attr "type"
!   "unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt,trap,atomic"
    (const_string "unknown"))
  
  ;; Main data type used by the insn
diff -Nrcpad gcc-15-20250913/gcc/config/microblaze/sync.md gcc-15-20250920/gcc/config/microblaze/sync.md
*** gcc-15-20250913/gcc/config/microblaze/sync.md	Sat Sep 13 22:32:06 2025
--- gcc-15-20250920/gcc/config/microblaze/sync.md	Sat Sep 20 22:32:28 2025
***************
*** 18,43 ****
  ;; <http://www.gnu.org/licenses/>.
  
  (define_insn "atomic_compare_and_swapsi"
!   [(match_operand:SI 0 "register_operand" "=&d")	;; bool output
!    (match_operand:SI 1 "register_operand" "=&d")	;; val output
!    (match_operand:SI 2 "nonimmediate_operand" "+Q")	;; memory
!    (match_operand:SI 3 "register_operand" "d")		;; expected value
!    (match_operand:SI 4 "register_operand" "d")		;; desired value
!    (match_operand:SI 5 "const_int_operand" "")		;; is_weak
!    (match_operand:SI 6 "const_int_operand" "")		;; mod_s
!    (match_operand:SI 7 "const_int_operand" "")		;; mod_f
     (clobber (match_scratch:SI 8 "=&d"))]
    ""
    {
!     output_asm_insn ("addc \tr0,r0,r0", operands);
!     output_asm_insn ("lwx  \t%1,%y2,r0", operands);
!     output_asm_insn ("addic\t%8,r0,0", operands);
!     output_asm_insn ("bnei \t%8,.-8", operands);
!     output_asm_insn ("cmp  \t%0,%1,%3", operands);
!     output_asm_insn ("bnei \t%0,.+16", operands);
!     output_asm_insn ("swx  \t%4,%y2,r0", operands);
!     output_asm_insn ("addic\t%8,r0,0", operands);
!     output_asm_insn ("bnei \t%8,.-28", operands);
!     return "";
    }
  )
--- 18,114 ----
  ;; <http://www.gnu.org/licenses/>.
  
  (define_insn "atomic_compare_and_swapsi"
!   [(set (match_operand:SI 0 "register_operand" "=&d")		;; bool output
!         (unspec_volatile:SI
!           [(match_operand:SI 2 "nonimmediate_operand" "+Q")	;; memory
!            (match_operand:SI 3 "register_operand" "d")		;; expected value
!            (match_operand:SI 4 "register_operand" "d")]		;; desired value
!           UNSPECV_CAS_BOOL))
!    (set (match_operand:SI 1 "register_operand" "=&d")		;; val output
!         (unspec_volatile:SI [(const_int 0)] UNSPECV_CAS_VAL))
!    (set (match_dup 2)
!         (unspec_volatile:SI [(const_int 0)] UNSPECV_CAS_MEM))
!    (match_operand:SI 5 "const_int_operand" "")			;; is_weak
!    (match_operand:SI 6 "const_int_operand" "")			;; mod_s
!    (match_operand:SI 7 "const_int_operand" "")			;; mod_f
     (clobber (match_scratch:SI 8 "=&d"))]
    ""
    {
!     return "add  \t%0,r0,r0\n\t"
!       "lwx  \t%1,%y2,r0\n\t"
!       "addic\t%8,r0,0\n\t"
!       "bnei \t%8,.-8\n\t"
!       "cmp  \t%8,%1,%3\n\t"
!       "bnei \t%8,.+20\n\t"
!       "swx  \t%4,%y2,r0\n\t"
!       "addic\t%8,r0,0\n\t"
!       "bnei \t%8,.-28\n\t"
!       "addi \t%0,r0,1";
    }
+   [(set_attr "type"	"atomic")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"40")]
  )
+ 
+ ;;
+ ;;
+ ;;
+ ;;
+ (define_insn "atomic_fetch_<atomic_optab>si"
+   [(set (match_operand:SI 0 "register_operand" "=&d")
+ 	(match_operand:SI 1 "memory_operand" "+Q"))
+    (set (match_dup 1)
+ 	(unspec_volatile:SI
+ 	  [(any_atomic:SI (match_dup 1)
+ 		   (match_operand:SI 2 "register_operand" "d"))
+ 	   (match_operand:SI 3 "const_int_operand")] ;; model
+ 	 UNSPECV_ATOMIC_FETCH_OP))
+    (clobber (match_scratch:SI 4 "=&d"))]	  ;; tmp_1
+   ""
+   {
+     return
+       "lwx  \t%0,%y1,r0\n\t"
+       "addic\t%4,r0,0\n\t"
+       "bnei \t%4,.-8\n\t"
+       "<atomic_optab>\t%4,%0,%2\n\t"
+       "swx  \t%4,%y1,r0\n\t"
+       "addic\t%4,r0,0\n\t"
+       "bnei \t%4,.-24";
+   }
+   [(set_attr "type"	"atomic")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"28")])
+ 
+ ;;
+ ;; MicroBlaze only supports lx/sx instructions for word mode only
+ ;;
+ ;; Use shift|mask magic to implement atomic_test_and_set using lwx/swx
+ ;;
+ (define_expand "atomic_test_and_set"
+   [(match_operand:QI 0 "register_operand" "")    ;; bool output
+    (match_operand:QI 1 "memory_operand" "m")    ;; memory
+    (match_operand:SI 2 "const_int_operand" "")]  ;; model
+   ""
+ {
+   rtx old = gen_reg_rtx (SImode);
+   rtx mem = operands[1];
+   rtx model = operands[2];
+   rtx set = gen_reg_rtx (SImode);
+   rtx aligned_mem = gen_reg_rtx (SImode);
+   rtx shift = gen_reg_rtx (SImode);
+ 
+   microblaze_subword_address (mem, &aligned_mem, &shift);
+ 
+   emit_move_insn (set, GEN_INT (1));
+   rtx shifted_set = gen_reg_rtx (SImode);
+ 
+   emit_move_insn (shifted_set, gen_rtx_ASHIFT (SImode, set, shift));
+ 
+   emit_insn (gen_atomic_fetch_orsi (old, aligned_mem, shifted_set, model));
+ 
+   emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old, shift));
+ 
+   emit_move_insn (operands[0], gen_lowpart (QImode, old));
+ 
+   DONE;
+ })
diff -Nrcpad gcc-15-20250913/gcc/cp/ChangeLog gcc-15-20250920/gcc/cp/ChangeLog
*** gcc-15-20250913/gcc/cp/ChangeLog	Sat Sep 13 22:32:06 2025
--- gcc-15-20250920/gcc/cp/ChangeLog	Sat Sep 20 22:32:28 2025
***************
*** 1,3 ****
--- 1,12 ----
+ 2025-09-15  Matthias Kretz  <m.kretz@gsi.de>
+ 
+ 	Backported from master:
+ 	2025-09-09  Matthias Kretz  <m.kretz@gsi.de>
+ 
+ 	PR c++/121801
+ 	* mangle.cc (write_real_cst): Handle 16-bit real and assert
+ 	that reals have 16 bits or a multiple of 32 bits.
+ 
  2025-09-12  Patrick Palka  <ppalka@redhat.com>
  
  	Backported from master:
diff -Nrcpad gcc-15-20250913/gcc/cp/mangle.cc gcc-15-20250920/gcc/cp/mangle.cc
*** gcc-15-20250913/gcc/cp/mangle.cc	Sat Sep 13 22:32:06 2025
--- gcc-15-20250920/gcc/cp/mangle.cc	Sat Sep 20 22:32:28 2025
*************** write_real_cst (const tree value)
*** 2161,2171 ****
    int i, limit, dir;
  
    tree type = TREE_TYPE (value);
!   int words = GET_MODE_BITSIZE (SCALAR_FLOAT_TYPE_MODE (type)) / 32;
  
    real_to_target (target_real, &TREE_REAL_CST (value),
  		  TYPE_MODE (type));
  
    /* The value in target_real is in the target word order,
       so we must write it out backward if that happens to be
       little-endian.  write_number cannot be used, it will
--- 2161,2184 ----
    int i, limit, dir;
  
    tree type = TREE_TYPE (value);
!   int bits = GET_MODE_BITSIZE (SCALAR_FLOAT_TYPE_MODE (type));
!   int words = bits / 32;
  
    real_to_target (target_real, &TREE_REAL_CST (value),
  		  TYPE_MODE (type));
  
+   if (words == 0)
+     {
+       /* _Float16 and std::bfloat16_t are the only supported types smaller than
+ 	 32 bits.  */
+       gcc_assert (bits == 16);
+       sprintf (buffer, "%04lx", (unsigned long) target_real[0]);
+       write_chars (buffer, 4);
+       return;
+     }
+ 
+   gcc_assert (bits % 32 == 0);
+ 
    /* The value in target_real is in the target word order,
       so we must write it out backward if that happens to be
       little-endian.  write_number cannot be used, it will
diff -Nrcpad gcc-15-20250913/gcc/doc/avr-mmcu.texi gcc-15-20250920/gcc/doc/avr-mmcu.texi
*** gcc-15-20250913/gcc/doc/avr-mmcu.texi	Sat Sep 13 22:32:07 2025
--- gcc-15-20250920/gcc/doc/avr-mmcu.texi	Sat Sep 20 22:32:28 2025
***************
*** 54,60 ****
  
  @item @anchor{avrxmega3}avrxmega3
  ``XMEGA'' devices with up to 64@tie{}KiB of combined program memory and RAM, and with program memory visible in the RAM address space.
! @*@var{mcu}@tie{}= @code{attiny202}, @code{attiny204}, @code{attiny212}, @code{attiny214}, @code{attiny402}, @code{attiny404}, @code{attiny406}, @code{attiny412}, @code{attiny414}, @code{attiny416}, @code{attiny416auto}, @code{attiny417}, @code{attiny424}, @code{attiny426}, @code{attiny427}, @code{attiny804}, @code{attiny806}, @code{attiny807}, @code{attiny814}, @code{attiny816}, @code{attiny817}, @code{attiny824}, @code{attiny826}, @code{attiny827}, @code{attiny1604}, @code{attiny1606}, @code{attiny1607}, @code{attiny1614}, @code{attiny1616}, @code{attiny1617}, @code{attiny1624}, @code{attiny1626}, @code{attiny1627}, @code{attiny3214}, @code{attiny3216}, @code{attiny3217}, @code{attiny3224}, @code{attiny3226}, @code{attiny3227}, @code{atmega808}, @code{atmega809}, @code{atmega1608}, @code{atmega1609}, @code{atmega3208}, @code{atmega3209}, @code{atmega4808}, @code{atmega4809}, @code{avr16dd14}, @code{avr16dd20}, @code{avr16dd28}, @code{avr16dd32}, @code{avr16du14}, @code{avr16du20}, @code{avr16du28}, @code{avr16du32}, @code{avr16ea28}, @code{avr16ea32}, @code{avr16ea48}, @code{avr16eb14}, @code{avr16eb20}, @code{avr16eb28}, @code{avr16eb32}, @code{avr32da28}, @code{avr32da28s}, @code{avr32da32}, @code{avr32da32s}, @code{avr32da48}, @code{avr32da48s}, @code{avr32db28}, @code{avr32db32}, @code{avr32db48}, @code{avr32dd14}, @code{avr32dd20}, @code{avr32dd28}, @code{avr32dd32}, @code{avr32du14}, @code{avr32du20}, @code{avr32du28}, @code{avr32du32}, @code{avr32ea28}, @code{avr32ea32}, @code{avr32ea48}, @code{avr32sd20}, @code{avr32sd28}, @code{avr32sd32}.
  
  @item @anchor{avrxmega4}avrxmega4
  ``XMEGA'' devices with more than 64@tie{}KiB and up to 128@tie{}KiB of program memory.
--- 54,60 ----
  
  @item @anchor{avrxmega3}avrxmega3
  ``XMEGA'' devices with up to 64@tie{}KiB of combined program memory and RAM, and with program memory visible in the RAM address space.
! @*@var{mcu}@tie{}= @code{attiny202}, @code{attiny204}, @code{attiny212}, @code{attiny214}, @code{attiny402}, @code{attiny404}, @code{attiny406}, @code{attiny412}, @code{attiny414}, @code{attiny416}, @code{attiny416auto}, @code{attiny417}, @code{attiny424}, @code{attiny426}, @code{attiny427}, @code{attiny804}, @code{attiny806}, @code{attiny807}, @code{attiny814}, @code{attiny816}, @code{attiny817}, @code{attiny824}, @code{attiny826}, @code{attiny827}, @code{attiny1604}, @code{attiny1606}, @code{attiny1607}, @code{attiny1614}, @code{attiny1616}, @code{attiny1617}, @code{attiny1624}, @code{attiny1626}, @code{attiny1627}, @code{attiny3214}, @code{attiny3216}, @code{attiny3217}, @code{attiny3224}, @code{attiny3226}, @code{attiny3227}, @code{atmega808}, @code{atmega809}, @code{atmega1608}, @code{atmega1609}, @code{atmega3208}, @code{atmega3209}, @code{atmega4808}, @code{atmega4809}, @code{avr16dd14}, @code{avr16dd20}, @code{avr16dd28}, @code{avr16dd32}, @code{avr16du14}, @code{avr16du20}, @code{avr16du28}, @code{avr16du32}, @code{avr16ea28}, @code{avr16ea32}, @code{avr16ea48}, @code{avr16eb14}, @code{avr16eb20}, @code{avr16eb28}, @code{avr16eb32}, @code{avr32da28}, @code{avr32da28s}, @code{avr32da32}, @code{avr32da32s}, @code{avr32da48}, @code{avr32da48s}, @code{avr32db28}, @code{avr32db32}, @code{avr32db48}, @code{avr32dd14}, @code{avr32dd20}, @code{avr32dd28}, @code{avr32dd32}, @code{avr32du14}, @code{avr32du20}, @code{avr32du28}, @code{avr32du32}, @code{avr32ea28}, @code{avr32ea32}, @code{avr32ea48}, @code{avr32eb14}, @code{avr32eb20}, @code{avr32eb28}, @code{avr32eb32}, @code{avr32sd20}, @code{avr32sd28}, @code{avr32sd32}.
  
  @item @anchor{avrxmega4}avrxmega4
  ``XMEGA'' devices with more than 64@tie{}KiB and up to 128@tie{}KiB of program memory.
diff -Nrcpad gcc-15-20250913/gcc/lra-constraints.cc gcc-15-20250920/gcc/lra-constraints.cc
*** gcc-15-20250913/gcc/lra-constraints.cc	Sat Sep 13 22:32:07 2025
--- gcc-15-20250920/gcc/lra-constraints.cc	Sat Sep 20 22:32:28 2025
*************** get_equiv (rtx x)
*** 541,546 ****
--- 541,547 ----
    rtx res;
  
    if (! REG_P (x) || (regno = REGNO (x)) < FIRST_PSEUDO_REGISTER
+       || regno >= ira_reg_equiv_len
        || ! ira_reg_equiv[regno].defined_p
        || ! ira_reg_equiv[regno].profitable_p
        || lra_get_regno_hard_regno (regno) >= 0)
diff -Nrcpad gcc-15-20250913/gcc/testsuite/ChangeLog gcc-15-20250920/gcc/testsuite/ChangeLog
*** gcc-15-20250913/gcc/testsuite/ChangeLog	Sat Sep 13 22:32:07 2025
--- gcc-15-20250920/gcc/testsuite/ChangeLog	Sat Sep 20 22:32:29 2025
***************
*** 1,3 ****
--- 1,80 ----
+ 2025-09-18  hongtao.liu  <hongtao.liu@intel.com>
+ 
+ 	Backported from master:
+ 	2025-09-18  hongtao.liu  <hongtao.liu@intel.com>
+ 
+ 	* gcc.target/i386/pieces-memcpy-18.c: Use -mtune=znver5
+ 	instead of -mtune=sapphirerapids.
+ 	* gcc.target/i386/pieces-memcpy-21.c: Ditto.
+ 	* gcc.target/i386/pieces-memset-46.c: Ditto.
+ 	* gcc.target/i386/pieces-memset-49.c: Ditto.
+ 
+ 2025-09-17  Torbjörn SVENSSON  <torbjorn.svensson@foss.st.com>
+ 
+ 	Backported from master:
+ 	2025-09-17  Torbjörn SVENSSON  <torbjorn.svensson@foss.st.com>
+ 
+ 	* gcc.target/arm/fp16-aapcs.c: New test.
+ 	* gcc.target/arm/fp16-aapcs-1.c: Removed.
+ 	* gcc.target/arm/fp16-aapcs-2.c: Likewise.
+ 	* gcc.target/arm/fp16-aapcs-3.c: Likewise.
+ 	* gcc.target/arm/fp16-aapcs-4.c: Likewise.
+ 
+ 2025-09-16  Jennifer Schmitz  <jschmitz@nvidia.com>
+ 
+ 	PR target/121602
+ 	* gcc.target/aarch64/sve/acle/asm/mul_s16.c: New test.
+ 	* gcc.target/aarch64/sve/acle/asm/mul_s32.c: Likewise.
+ 	* gcc.target/aarch64/sve/acle/asm/mul_s64.c: Likewise.
+ 	* gcc.target/aarch64/sve/acle/asm/mul_s8.c: Likewise.
+ 	* gcc.target/aarch64/sve/acle/asm/mul_u16.c: Likewise.
+ 	* gcc.target/aarch64/sve/acle/asm/mul_u32.c: Likewise.
+ 	* gcc.target/aarch64/sve/acle/asm/mul_u64.c: Likewise.
+ 	* gcc.target/aarch64/sve/acle/asm/mul_u8.c: Likewise.
+ 
+ 2025-09-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+ 
+ 	Backported from master:
+ 	2025-08-11  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+ 
+ 	PR target/121464
+ 	* gcc.target/arm/acle/mcrr.c: Update testcase.
+ 	* gcc.target/arm/acle/mcrr2.c: Likewise.
+ 	* gcc.target/arm/acle/mrrc.c: Likewise.
+ 	* gcc.target/arm/acle/mrrc2.c: Likewise.
+ 
+ 2025-09-15  Kyrylo Tkachov  <ktkachov@nvidia.com>
+ 
+ 	Backported from master:
+ 	2025-09-03  Kyrylo Tkachov  <ktkachov@nvidia.com>
+ 
+ 	PR target/121749
+ 	* gcc.target/aarch64/simd/pr121749.c: Use dg-assemble directive.
+ 
+ 2025-09-15  Kyrylo Tkachov  <ktkachov@nvidia.com>
+ 
+ 	Backported from master:
+ 	2025-09-03  Kyrylo Tkachov  <ktkachov@nvidia.com>
+ 
+ 	PR target/121749
+ 	* gcc.target/aarch64/simd/pr121749.c: New test.
+ 
+ 2025-09-15  Xi Ruoyao  <xry111@xry111.site>
+ 
+ 	Backported from master:
+ 	2025-09-15  Xi Ruoyao  <xry111@xry111.site>
+ 
+ 	PR target/121906
+ 	* gcc.target/loongarch/pr121906.c: New test.
+ 
+ 2025-09-15  Matthias Kretz  <m.kretz@gsi.de>
+ 
+ 	Backported from master:
+ 	2025-09-09  Matthias Kretz  <m.kretz@gsi.de>
+ 
+ 	PR c++/121801
+ 	* g++.dg/abi/pr121801.C: New test.
+ 
  2025-09-12  Patrick Palka  <ppalka@redhat.com>
  
  	Backported from master:
diff -Nrcpad gcc-15-20250913/gcc/testsuite/g++.dg/abi/pr121801.C gcc-15-20250920/gcc/testsuite/g++.dg/abi/pr121801.C
*** gcc-15-20250913/gcc/testsuite/g++.dg/abi/pr121801.C	Thu Jan  1 00:00:00 1970
--- gcc-15-20250920/gcc/testsuite/g++.dg/abi/pr121801.C	Sat Sep 20 22:32:31 2025
***************
*** 0 ****
--- 1,13 ----
+ // PR c++/121801
+ // { dg-do compile { target { c++20 && float16 } } }
+ // { dg-add-options float16 }
+ 
+ template<_Float16 T> void f() {}
+ 
+ void uses() {
+   f<_Float16(1)>();
+   f<_Float16(2)>();
+ }
+ 
+ // { dg-final { scan-assembler "_Z1fILDF16_3c00EEvv" } }
+ // { dg-final { scan-assembler "_Z1fILDF16_4000EEvv" } }
diff -Nrcpad gcc-15-20250913/gcc/testsuite/gcc.target/aarch64/simd/pr121749.c gcc-15-20250920/gcc/testsuite/gcc.target/aarch64/simd/pr121749.c
*** gcc-15-20250913/gcc/testsuite/gcc.target/aarch64/simd/pr121749.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20250920/gcc/testsuite/gcc.target/aarch64/simd/pr121749.c	Sat Sep 20 22:33:01 2025
***************
*** 0 ****
--- 1,11 ----
+ /* { dg-do assemble } */
+ /* { dg-options "-O2" } */
+ 
+ #include <arm_neon.h>
+ 
+ uint32_t
+ foo (uint64_t v0)
+ {
+   return vqshrnd_n_u64 (vshrd_n_u64 (v0, 26), 7);
+ }
+ 
diff -Nrcpad gcc-15-20250913/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s16.c gcc-15-20250920/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s16.c
*** gcc-15-20250913/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s16.c	Sat Sep 13 22:32:21 2025
--- gcc-15-20250920/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s16.c	Sat Sep 20 22:33:03 2025
*************** TEST_UNIFORM_Z (mul_1op1_s16_z_tied2, sv
*** 332,337 ****
--- 332,347 ----
  		z0 = svmul_z (p0, svdup_s16 (1), z0))
  
  /*
+ ** mul_1op1n_s16_z:
+ **	movprfx	z0\.h, p0/z, z0\.h
+ **	mov	z0\.h, p0/m, w0
+ **	ret
+ */
+ TEST_UNIFORM_ZX (mul_1op1n_s16_z, svint16_t, int16_t,
+ 	z0 = svmul_n_s16_z (p0, svdup_s16 (1), x0),
+ 	z0 = svmul_z (p0, svdup_s16 (1), x0))
+ 
+ /*
  ** mul_3_s16_z_tied1:
  **	mov	(z[0-9]+\.h), #3
  **	movprfx	z0\.h, p0/z, z0\.h
diff -Nrcpad gcc-15-20250913/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s32.c gcc-15-20250920/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s32.c
*** gcc-15-20250913/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s32.c	Sat Sep 13 22:32:21 2025
--- gcc-15-20250920/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s32.c	Sat Sep 20 22:33:03 2025
*************** TEST_UNIFORM_Z (mul_1op1_s32_z_tied2, sv
*** 342,347 ****
--- 342,357 ----
  		z0 = svmul_z (p0, svdup_s32 (1), z0))
  
  /*
+ ** mul_1op1n_s32_z:
+ **	movprfx	z0\.s, p0/z, z0\.s
+ **	mov	z0\.s, p0/m, w0
+ **	ret
+ */
+ TEST_UNIFORM_ZX (mul_1op1n_s32_z, svint32_t, int32_t,
+ 	z0 = svmul_n_s32_z (p0, svdup_s32 (1), x0),
+ 	z0 = svmul_z (p0, svdup_s32 (1), x0))
+ 
+ /*
  ** mul_3_s32_z_tied1:
  **	mov	(z[0-9]+\.s), #3
  **	movprfx	z0\.s, p0/z, z0\.s
diff -Nrcpad gcc-15-20250913/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s64.c gcc-15-20250920/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s64.c
*** gcc-15-20250913/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s64.c	Sat Sep 13 22:32:21 2025
--- gcc-15-20250920/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s64.c	Sat Sep 20 22:33:03 2025
*************** TEST_UNIFORM_Z (mul_1op1_s64_z_tied2, sv
*** 341,346 ****
--- 341,356 ----
  		z0 = svmul_z (p0, svdup_s64 (1), z0))
  
  /*
+ ** mul_1op1n_s64_z:
+ **	movprfx	z0\.d, p0/z, z0\.d
+ **	mov	z0\.d, p0/m, x0
+ **	ret
+ */
+ TEST_UNIFORM_ZX (mul_1op1n_s64_z, svint64_t, int64_t,
+ 	z0 = svmul_n_s64_z (p0, svdup_s64 (1), x0),
+ 	z0 = svmul_z (p0, svdup_s64 (1), x0))
+ 
+ /*
  ** mul_2_s64_z_tied1:
  **	movprfx	z0.d, p0/z, z0.d
  **	lsl	z0.d, p0/m, z0.d, #1
diff -Nrcpad gcc-15-20250913/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s8.c gcc-15-20250920/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s8.c
*** gcc-15-20250913/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s8.c	Sat Sep 13 22:32:21 2025
--- gcc-15-20250920/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s8.c	Sat Sep 20 22:33:03 2025
*************** TEST_UNIFORM_Z (mul_1op1_s8_z_tied2, svi
*** 332,337 ****
--- 332,347 ----
  		z0 = svmul_z (p0, svdup_s8 (1), z0))
  
  /*
+ ** mul_1op1n_s8_z:
+ **	movprfx	z0\.b, p0/z, z0\.b
+ **	mov	z0\.b, p0/m, w0
+ **	ret
+ */
+ TEST_UNIFORM_ZX (mul_1op1n_s8_z, svint8_t, int8_t,
+ 	z0 = svmul_n_s8_z (p0, svdup_s8 (1), x0),
+ 	z0 = svmul_z (p0, svdup_s8 (1), x0))
+ 
+ /*
  ** mul_3_s8_z_tied1:
  **	mov	(z[0-9]+\.b), #3
  **	movprfx	z0\.b, p0/z, z0\.b
diff -Nrcpad gcc-15-20250913/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u16.c gcc-15-20250920/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u16.c
*** gcc-15-20250913/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u16.c	Sat Sep 13 22:32:21 2025
--- gcc-15-20250920/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u16.c	Sat Sep 20 22:33:03 2025
*************** TEST_UNIFORM_Z (mul_1op1_u16_z_tied2, sv
*** 313,318 ****
--- 313,328 ----
  		z0 = svmul_z (p0, svdup_u16 (1), z0))
  
  /*
+ ** mul_1op1n_u16_z:
+ **	movprfx	z0\.h, p0/z, z0\.h
+ **	mov	z0\.h, p0/m, w0
+ **	ret
+ */
+ TEST_UNIFORM_ZX (mul_1op1n_u16_z, svuint16_t, uint16_t,
+ 	z0 = svmul_n_u16_z (p0, svdup_u16 (1), x0),
+ 	z0 = svmul_z (p0, svdup_u16 (1), x0))
+ 
+ /*
  ** mul_3_u16_z_tied1:
  **	mov	(z[0-9]+\.h), #3
  **	movprfx	z0\.h, p0/z, z0\.h
diff -Nrcpad gcc-15-20250913/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u32.c gcc-15-20250920/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u32.c
*** gcc-15-20250913/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u32.c	Sat Sep 13 22:32:21 2025
--- gcc-15-20250920/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u32.c	Sat Sep 20 22:33:03 2025
*************** TEST_UNIFORM_Z (mul_1op1_u32_z_tied2, sv
*** 313,318 ****
--- 313,328 ----
  		z0 = svmul_z (p0, svdup_u32 (1), z0))
  
  /*
+ ** mul_1op1n_u32_z:
+ **	movprfx	z0\.s, p0/z, z0\.s
+ **	mov	z0\.s, p0/m, w0
+ **	ret
+ */
+ TEST_UNIFORM_ZX (mul_1op1n_u32_z, svuint32_t, uint32_t,
+ 	z0 = svmul_n_u32_z (p0, svdup_u32 (1), x0),
+ 	z0 = svmul_z (p0, svdup_u32 (1), x0))
+ 
+ /*
  ** mul_3_u32_z_tied1:
  **	mov	(z[0-9]+\.s), #3
  **	movprfx	z0\.s, p0/z, z0\.s
diff -Nrcpad gcc-15-20250913/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u64.c gcc-15-20250920/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u64.c
*** gcc-15-20250913/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u64.c	Sat Sep 13 22:32:21 2025
--- gcc-15-20250920/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u64.c	Sat Sep 20 22:33:03 2025
*************** TEST_UNIFORM_Z (mul_1op1_u64_z_tied2, sv
*** 334,339 ****
--- 334,349 ----
  		z0 = svmul_z (p0, svdup_u64 (1), z0))
  
  /*
+ ** mul_1op1n_u64_z:
+ **	movprfx	z0\.d, p0/z, z0\.d
+ **	mov	z0\.d, p0/m, x0
+ **	ret
+ */
+ TEST_UNIFORM_ZX (mul_1op1n_u64_z, svuint64_t, uint64_t,
+ 	z0 = svmul_n_u64_z (p0, svdup_u64 (1), x0),
+ 	z0 = svmul_z (p0, svdup_u64 (1), x0))
+ 
+ /*
  ** mul_2_u64_z_tied1:
  **	movprfx	z0.d, p0/z, z0.d
  **	lsl	z0.d, p0/m, z0.d, #1
diff -Nrcpad gcc-15-20250913/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u8.c gcc-15-20250920/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u8.c
*** gcc-15-20250913/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u8.c	Sat Sep 13 22:32:21 2025
--- gcc-15-20250920/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u8.c	Sat Sep 20 22:33:03 2025
*************** TEST_UNIFORM_Z (mul_1op1_u8_z_tied2, svu
*** 313,318 ****
--- 313,328 ----
  		z0 = svmul_z (p0, svdup_u8 (1), z0))
  
  /*
+ ** mul_1op1n_u8_z:
+ **	movprfx	z0\.b, p0/z, z0\.b
+ **	mov	z0\.b, p0/m, w0
+ **	ret
+ */
+ TEST_UNIFORM_ZX (mul_1op1n_u8_z, svuint8_t, uint8_t,
+ 	z0 = svmul_n_u8_z (p0, svdup_u8 (1), x0),
+ 	z0 = svmul_z (p0, svdup_u8 (1), x0))
+ 
+ /*
  ** mul_3_u8_z_tied1:
  **	mov	(z[0-9]+\.b), #3
  **	movprfx	z0\.b, p0/z, z0\.b
diff -Nrcpad gcc-15-20250913/gcc/testsuite/gcc.target/arm/acle/mcrr.c gcc-15-20250920/gcc/testsuite/gcc.target/arm/acle/mcrr.c
*** gcc-15-20250913/gcc/testsuite/gcc.target/arm/acle/mcrr.c	Sat Sep 13 22:32:22 2025
--- gcc-15-20250920/gcc/testsuite/gcc.target/arm/acle/mcrr.c	Sat Sep 20 22:33:14 2025
***************
*** 3,8 ****
--- 3,9 ----
  /* { dg-do assemble } */
  /* { dg-options "-save-temps" } */
  /* { dg-require-effective-target arm_coproc3_ok } */
+ /* { dg-final { check-function-bodies "**" "" "" } } */
  
  #include "arm_acle.h"
  #if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \
*************** void test_mcrr (uint64_t a)
*** 15,20 ****
    a += 77;
    __arm_mcrr (10, 5, a, 3);
  }
  
! /* { dg-final { scan-assembler "add\[^\n\]*#77\n" } } */
! /* { dg-final { scan-assembler "mcrr\tp10, #5, r\[r0-9\]*, r\[r0-9\]*, CR3\n" } } */
--- 16,37 ----
    a += 77;
    __arm_mcrr (10, 5, a, 3);
  }
+ /*
+ ** test_mcrr:
+ ** ...
+ **	add.*#77
+ ** ...
+ **	mcrr	p10, #5, r[0-9]+, r[0-9]+, CR3
+ ** ...
+ */
  
! void test_mcrr_pr121464 (uint64_t a)
! {
!   __arm_mcrr (7, 11, a, 0);
! }
! /*
! ** test_mcrr_pr121464:
! ** ...
! **	mcrr	p7, #11, r[0-9]+, r[0-9]+, CR0
! ** ...
! */
diff -Nrcpad gcc-15-20250913/gcc/testsuite/gcc.target/arm/acle/mcrr2.c gcc-15-20250920/gcc/testsuite/gcc.target/arm/acle/mcrr2.c
*** gcc-15-20250913/gcc/testsuite/gcc.target/arm/acle/mcrr2.c	Sat Sep 13 22:32:22 2025
--- gcc-15-20250920/gcc/testsuite/gcc.target/arm/acle/mcrr2.c	Sat Sep 20 22:33:14 2025
***************
*** 3,8 ****
--- 3,9 ----
  /* { dg-do assemble } */
  /* { dg-options "-save-temps" } */
  /* { dg-require-effective-target arm_coproc4_ok } */
+ /* { dg-final { check-function-bodies "**" "" "" } } */
  
  #include "arm_acle.h"
  #if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \
*************** void test_mcrr2 (uint64_t a)
*** 15,20 ****
    a += 77;
    __arm_mcrr2 (10, 5, a, 3);
  }
  
! /* { dg-final { scan-assembler "add\[^\n\]*#77\n" } } */
! /* { dg-final { scan-assembler "mcrr2\tp10, #5, r\[r0-9\]*, r\[r0-9\]*, CR3\n" } } */
--- 16,40 ----
    a += 77;
    __arm_mcrr2 (10, 5, a, 3);
  }
+ /*
+ ** test_mcrr2:
+ ** ...
+ **	add.*#77
+ ** ...
+ **	mcrr2	p10, #5, r[0-9]+, r[0-9]+, CR3
+ ** ...
+ */
  
! void test_mcrr2_pr121464 (void)
! {
!   __arm_mcrr2 (3, 12, 49, 4);
! }
! 
! /*
! ** test_mcrr2_pr121464:
! ** ...
! **	mov.*#49
! ** ...
! **	mcrr2	p3, #12, r[0-9]+, r[0-9]+, CR4
! ** ...
! */
diff -Nrcpad gcc-15-20250913/gcc/testsuite/gcc.target/arm/acle/mrrc.c gcc-15-20250920/gcc/testsuite/gcc.target/arm/acle/mrrc.c
*** gcc-15-20250913/gcc/testsuite/gcc.target/arm/acle/mrrc.c	Sat Sep 13 22:32:22 2025
--- gcc-15-20250920/gcc/testsuite/gcc.target/arm/acle/mrrc.c	Sat Sep 20 22:33:14 2025
***************
*** 3,8 ****
--- 3,9 ----
  /* { dg-do assemble } */
  /* { dg-options "-save-temps" } */
  /* { dg-require-effective-target arm_coproc3_ok } */
+ /* { dg-final { check-function-bodies "**" "" "" } } */
  
  #include "arm_acle.h"
  #if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \
*************** uint64_t test_mrrc (void)
*** 15,18 ****
    return __arm_mrrc (10, 5, 3);
  }
  
! /* { dg-final { scan-assembler "mrrc\tp10, #5, r\[r0-9\]*, r\[r0-9\]*, CR3\n" } } */
--- 16,36 ----
    return __arm_mrrc (10, 5, 3);
  }
  
! /*
! ** test_mrrc:
! ** ...
! **	mrrc	p10, #5, r[0-9]+, r[0-9]+, CR3
! ** ...
! */
! 
! uint64_t test_mrrc_pr121464 (void)
! {
!   return __arm_mrrc (15, 9, 7);
! }
! 
! /*
! ** test_mrrc_pr121464:
! ** ...
! **	mrrc	p15, #9, r[0-9]+, r[0-9]+, CR7
! ** ...
! */
diff -Nrcpad gcc-15-20250913/gcc/testsuite/gcc.target/arm/acle/mrrc2.c gcc-15-20250920/gcc/testsuite/gcc.target/arm/acle/mrrc2.c
*** gcc-15-20250913/gcc/testsuite/gcc.target/arm/acle/mrrc2.c	Sat Sep 13 22:32:22 2025
--- gcc-15-20250920/gcc/testsuite/gcc.target/arm/acle/mrrc2.c	Sat Sep 20 22:33:14 2025
***************
*** 3,8 ****
--- 3,9 ----
  /* { dg-do assemble } */
  /* { dg-options "-save-temps" } */
  /* { dg-require-effective-target arm_coproc4_ok } */
+ /* { dg-final { check-function-bodies "**" "" "" } } */
  
  #include "arm_acle.h"
  #if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \
*************** uint64_t test_mrrc2 (void)
*** 14,18 ****
  {
    return __arm_mrrc2 (10, 5, 3);
  }
  
! /* { dg-final { scan-assembler "mrrc2\tp10, #5, r\[r0-9\]*, r\[r0-9\]*, CR3\n" } } */
--- 15,34 ----
  {
    return __arm_mrrc2 (10, 5, 3);
  }
+ /*
+ ** test_mrrc2:
+ ** ...
+ **	mrrc2	p10, #5, r[0-9]+, r[0-9]+, CR3
+ ** ...
+ */
  
! uint64_t test_mrrc2_pr121464 (void)
! {
!   return __arm_mrrc2 (0, 15, 10);
! }
! /*
! ** test_mrrc2_pr121464:
! ** ...
! **	mrrc2	p0, #15, r[0-9]+, r[0-9]+, CR10
! ** ...
! */
diff -Nrcpad gcc-15-20250913/gcc/testsuite/gcc.target/arm/fp16-aapcs-1.c gcc-15-20250920/gcc/testsuite/gcc.target/arm/fp16-aapcs-1.c
*** gcc-15-20250913/gcc/testsuite/gcc.target/arm/fp16-aapcs-1.c	Sat Sep 13 22:32:22 2025
--- gcc-15-20250920/gcc/testsuite/gcc.target/arm/fp16-aapcs-1.c	Thu Jan  1 00:00:00 1970
***************
*** 1,65 ****
- /* { dg-do compile }  */
- /* { dg-require-effective-target arm_hard_vfp_ok }  */
- /* { dg-require-effective-target arm_fp16_ok } */
- /* { dg-options "-O2" }  */
- /* { dg-add-options arm_fp16_ieee } */
- /* { dg-final { check-function-bodies "**" "" "" } } */
- 
- /* Test __fp16 arguments and return value in registers (hard-float).  */
- 
- void
- swap (__fp16, __fp16);
- 
- /*
- ** F:
- ** ...
- ** (
- 
- Below block is for non-armv8.1
- ** (
- **	vmov\.f32	(s[3-9]|s1[0-5]), s0
- ** ...
- **	vmov\.f32	s0, s1
- ** ...
- **	vmov\.f32	s1, \1
- ** |
- **	vmov\.f32	(s[3-9]|s1[0-5]), s1
- ** ...
- **	vmov\.f32	s1, s0
- ** ...
- **	vmov\.f32	s0, \2
- ** )
- **	vstr\.32	s2, \[sp, #4\]	@ int
- **	bl	swap
- **	vldr\.32	s2, \[sp, #4\]	@ int
- **	vmov\.f32	s0, s2
- 
- ** |
- 
- Below block is for armv8.1
- ** (
- **	vmov	(s[3-9]|s1[0-5]), s0	@ __fp16
- ** ...
- **	vmov	s0, s1	@ __fp16
- ** ...
- **	vmov	s1, \3	@ __fp16
- ** |
- **	vmov	(s[3-9]|s1[0-5]), s1	@ __fp16
- ** ...
- **	vmov	s1, s0	@ __fp16
- ** ...
- **	vmov	s0, \4	@ __fp16
- ** )
- **	vstr\.32	s2, \[sp, #4\]	@ int
- **	bl	swap
- **	vldr\.16	s0, \[sp, #4\]
- 
- ** )
- ** ...
- */
- __fp16
- F (__fp16 a, __fp16 b, __fp16 c)
- {
-   swap (b, a);
-   return c;
- }
--- 0 ----
diff -Nrcpad gcc-15-20250913/gcc/testsuite/gcc.target/arm/fp16-aapcs-2.c gcc-15-20250920/gcc/testsuite/gcc.target/arm/fp16-aapcs-2.c
*** gcc-15-20250913/gcc/testsuite/gcc.target/arm/fp16-aapcs-2.c	Sat Sep 13 22:32:22 2025
--- gcc-15-20250920/gcc/testsuite/gcc.target/arm/fp16-aapcs-2.c	Thu Jan  1 00:00:00 1970
***************
*** 1,44 ****
- /* { dg-do compile }  */
- /* { dg-require-effective-target arm_fp16_ok } */
- /* { dg-options "-mfloat-abi=softfp -O2 -mno-long-calls" }  */
- /* { dg-add-options arm_fp16_ieee } */
- /* { dg-skip-if "incompatible float-abi" { arm*-*-* } { "-mfloat-abi=hard" } } */
- /* { dg-final { check-function-bodies "**" "" "" } } */
- 
- /* Test __fp16 arguments and return value in registers (softfp).  */
- 
- void
- swap (__fp16, __fp16);
- 
- /*
- ** F:
- ** ...
- ** (
- **	mov	r3, r0	@ __fp16
- ** ...
- **	mov	r0, r1	@ __fp16
- ** ...
- **	mov	r1, r3	@ __fp16
- ** |
- **	mov	r3, r1	@ __fp16
- ** ...
- **	mov	r1, r0	@ __fp16
- ** ...
- **	mov	r0, r3	@ __fp16
- ** )
- ** ...
- */
- /*
- ** F: { target arm_little_endian }
- ** ...
- **	str	r2, \[sp, #4\]
- **	bl	swap
- **	ldrh	r0, \[sp, #4\]	@ __fp16
- ** ...
- */
- __fp16
- F (__fp16 a, __fp16 b, __fp16 c)
- {
-   swap (b, a);
-   return c;
- }
--- 0 ----
diff -Nrcpad gcc-15-20250913/gcc/testsuite/gcc.target/arm/fp16-aapcs-3.c gcc-15-20250920/gcc/testsuite/gcc.target/arm/fp16-aapcs-3.c
*** gcc-15-20250913/gcc/testsuite/gcc.target/arm/fp16-aapcs-3.c	Sat Sep 13 22:32:22 2025
--- gcc-15-20250920/gcc/testsuite/gcc.target/arm/fp16-aapcs-3.c	Thu Jan  1 00:00:00 1970
***************
*** 1,65 ****
- /* { dg-do compile }  */
- /* { dg-require-effective-target arm_hard_vfp_ok }  */
- /* { dg-require-effective-target arm_fp16_alternative_ok } */
- /* { dg-options "-O2" }  */
- /* { dg-add-options arm_fp16_alternative } */
- /* { dg-final { check-function-bodies "**" "" "" } } */
- 
- /* Test __fp16 arguments and return value in registers (hard-float).  */
- 
- void
- swap (__fp16, __fp16);
- 
- /*
- ** F:
- ** ...
- ** (
- 
- Below block is for non-armv8.1
- ** (
- **	vmov\.f32	(s[3-9]|s1[0-5]), s0
- ** ...
- **	vmov\.f32	s0, s1
- ** ...
- **	vmov\.f32	s1, \1
- ** |
- **	vmov\.f32	(s[3-9]|s1[0-5]), s1
- ** ...
- **	vmov\.f32	s1, s0
- ** ...
- **	vmov\.f32	s0, \2
- ** )
- **	vstr\.32	s2, \[sp, #4\]	@ int
- **	bl	swap
- **	vldr\.32	s2, \[sp, #4\]	@ int
- **	vmov\.f32	s0, s2
- 
- ** |
- 
- Below block is for armv8.1
- ** (
- **	vmov	(s[3-9]|s1[0-5]), s0
- ** ...
- **	vmov	s0, s1
- ** ...
- **	vmov	s1, \3
- ** |
- **	vmov	(s[3-9]|s1[0-5]), s1
- ** ...
- **	vmov	s1, s0
- ** ...
- **	vmov	s0, \4
- ** )
- **	vstr\.32	s2, \[sp, #4\]	@ int
- **	bl	swap
- **	vldr\.16	s0, \[sp, #4\]
- 
- ** )
- ** ...
- */
- __fp16
- F (__fp16 a, __fp16 b, __fp16 c)
- {
-   swap (b, a);
-   return c;
- }
--- 0 ----
diff -Nrcpad gcc-15-20250913/gcc/testsuite/gcc.target/arm/fp16-aapcs-4.c gcc-15-20250920/gcc/testsuite/gcc.target/arm/fp16-aapcs-4.c
*** gcc-15-20250913/gcc/testsuite/gcc.target/arm/fp16-aapcs-4.c	Sat Sep 13 22:32:22 2025
--- gcc-15-20250920/gcc/testsuite/gcc.target/arm/fp16-aapcs-4.c	Thu Jan  1 00:00:00 1970
***************
*** 1,44 ****
- /* { dg-do compile }  */
- /* { dg-require-effective-target arm_fp16_alternative_ok } */
- /* { dg-options "-mfloat-abi=softfp -O2" }  */
- /* { dg-add-options arm_fp16_alternative } */
- /* { dg-skip-if "incompatible float-abi" { arm*-*-* } { "-mfloat-abi=hard" } } */
- /* { dg-final { check-function-bodies "**" "" "" } } */
- 
- /* Test __fp16 arguments and return value in registers (softfp).  */
- 
- void
- swap (__fp16, __fp16);
- 
- /*
- ** F:
- ** ...
- ** (
- **	mov	r3, r0	@ __fp16
- ** ...
- **	mov	r0, r1	@ __fp16
- ** ...
- **	mov	r1, r3	@ __fp16
- ** |
- **	mov	r3, r1	@ __fp16
- ** ...
- **	mov	r1, r0	@ __fp16
- ** ...
- **	mov	r0, r3	@ __fp16
- ** )
- ** ...
- */
- /*
- ** F: { target arm_little_endian }
- ** ...
- **	str	r2, \[sp, #4\]
- **	bl	swap
- **	ldrh	r0, \[sp, #4\]	@ __fp16
- ** ...
- */
- __fp16
- F (__fp16 a, __fp16 b, __fp16 c)
- {
-   swap (b, a);
-   return c;
- }
--- 0 ----
diff -Nrcpad gcc-15-20250913/gcc/testsuite/gcc.target/arm/fp16-aapcs.c gcc-15-20250920/gcc/testsuite/gcc.target/arm/fp16-aapcs.c
*** gcc-15-20250913/gcc/testsuite/gcc.target/arm/fp16-aapcs.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20250920/gcc/testsuite/gcc.target/arm/fp16-aapcs.c	Sat Sep 20 22:33:14 2025
***************
*** 0 ****
--- 1,24 ----
+ /* { dg-do compile }  */
+ /* { dg-require-effective-target arm_fp16_alternative_ok } */
+ /* { dg-options "-O2" }  */
+ /* { dg-add-options arm_fp16_alternative } */
+ /* { dg-final { check-function-bodies "**" "" "" } } */
+ 
+ /* Test __fp16 arguments and return value in registers.  */
+ 
+ __fp16 f();
+ void g(__fp16);
+ void h();
+ 
+ /*
+ ** test:
+ ** ...
+ **	bl	f
+ **	bl	g
+ ** ...
+ */
+ int test()
+ {
+     g(f());
+     h();
+ }
diff -Nrcpad gcc-15-20250913/gcc/testsuite/gcc.target/i386/pieces-memcpy-18.c gcc-15-20250920/gcc/testsuite/gcc.target/i386/pieces-memcpy-18.c
*** gcc-15-20250913/gcc/testsuite/gcc.target/i386/pieces-memcpy-18.c	Sat Sep 13 22:32:23 2025
--- gcc-15-20250920/gcc/testsuite/gcc.target/i386/pieces-memcpy-18.c	Sat Sep 20 22:33:18 2025
***************
*** 1,5 ****
  /* { dg-do compile } */
! /* { dg-options "-O2 -march=sapphirerapids" } */
  
  extern char *dst, *src;
  
--- 1,5 ----
  /* { dg-do compile } */
! /* { dg-options "-O2 -march=znver5" } */
  
  extern char *dst, *src;
  
diff -Nrcpad gcc-15-20250913/gcc/testsuite/gcc.target/i386/pieces-memcpy-21.c gcc-15-20250920/gcc/testsuite/gcc.target/i386/pieces-memcpy-21.c
*** gcc-15-20250913/gcc/testsuite/gcc.target/i386/pieces-memcpy-21.c	Sat Sep 13 22:32:23 2025
--- gcc-15-20250920/gcc/testsuite/gcc.target/i386/pieces-memcpy-21.c	Sat Sep 20 22:33:18 2025
***************
*** 1,5 ****
  /* { dg-do compile } */
! /* { dg-options "-O2 -mtune=sapphirerapids -march=x86-64 -mavx2" } */
  
  extern char *dst, *src;
  
--- 1,5 ----
  /* { dg-do compile } */
! /* { dg-options "-O2 -mtune=znver5 -march=x86-64 -mavx2" } */
  
  extern char *dst, *src;
  
diff -Nrcpad gcc-15-20250913/gcc/testsuite/gcc.target/i386/pieces-memset-46.c gcc-15-20250920/gcc/testsuite/gcc.target/i386/pieces-memset-46.c
*** gcc-15-20250913/gcc/testsuite/gcc.target/i386/pieces-memset-46.c	Sat Sep 13 22:32:23 2025
--- gcc-15-20250920/gcc/testsuite/gcc.target/i386/pieces-memset-46.c	Sat Sep 20 22:33:18 2025
***************
*** 1,5 ****
  /* { dg-do compile } */
! /* { dg-options "-O2 -march=sapphirerapids" } */
  
  extern char *dst;
  
--- 1,5 ----
  /* { dg-do compile } */
! /* { dg-options "-O2 -march=znver5" } */
  
  extern char *dst;
  
diff -Nrcpad gcc-15-20250913/gcc/testsuite/gcc.target/i386/pieces-memset-49.c gcc-15-20250920/gcc/testsuite/gcc.target/i386/pieces-memset-49.c
*** gcc-15-20250913/gcc/testsuite/gcc.target/i386/pieces-memset-49.c	Sat Sep 13 22:32:23 2025
--- gcc-15-20250920/gcc/testsuite/gcc.target/i386/pieces-memset-49.c	Sat Sep 20 22:33:18 2025
***************
*** 1,5 ****
  /* { dg-do compile } */
! /* { dg-options "-O2 -mtune=sapphirerapids -march=x86-64 -mavx2" } */
  
  extern char *dst;
  
--- 1,5 ----
  /* { dg-do compile } */
! /* { dg-options "-O2 -mtune=znver5 -march=x86-64 -mavx2" } */
  
  extern char *dst;
  
diff -Nrcpad gcc-15-20250913/gcc/testsuite/gcc.target/loongarch/pr121906.c gcc-15-20250920/gcc/testsuite/gcc.target/loongarch/pr121906.c
*** gcc-15-20250913/gcc/testsuite/gcc.target/loongarch/pr121906.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20250920/gcc/testsuite/gcc.target/loongarch/pr121906.c	Sat Sep 20 22:33:18 2025
***************
*** 0 ****
--- 1,31 ----
+ /* PR target/121906 */
+ /* { dg-do run } */
+ /* { dg-options "-O2 -mno-lsx" } */
+ 
+ typedef unsigned short u16;
+ typedef unsigned long u64;
+ typedef u16 v4hi __attribute__ ((vector_size (8)));
+ typedef u16 v8hi __attribute__ ((vector_size (16)));
+ 
+ u64 d;
+ int e, i;
+ u16 x;
+ 
+ int
+ main ()
+ {
+   v4hi n = { 1 };
+   u64 *o = &d;
+ p:
+   asm goto ("" : : : : q);
+   n[3] = (-(v8hi){ 0, 0, 0, 0, x })[7];
+   for (; e >= 0; e--)
+     {
+       *o = n[0];
+       if (i)
+         goto p;
+     q:
+     }
+   if (d != 1)
+     __builtin_trap ();
+ }
diff -Nrcpad gcc-15-20250913/libstdc++-v3/ChangeLog gcc-15-20250920/libstdc++-v3/ChangeLog
*** gcc-15-20250913/libstdc++-v3/ChangeLog	Sat Sep 13 22:32:56 2025
--- gcc-15-20250920/libstdc++-v3/ChangeLog	Sat Sep 20 22:33:45 2025
***************
*** 1,3 ****
--- 1,17 ----
+ 2025-09-18  Patrick Palka  <ppalka@redhat.com>
+ 
+ 	Backported from master:
+ 	2025-09-17  Patrick Palka  <ppalka@redhat.com>
+ 
+ 	* testsuite/20_util/bind/dangling_ref.cc: Compile with
+ 	-Wsystem-headers.
+ 	* testsuite/20_util/ratio/operations/ops_overflow_neg.cc: Likewise.
+ 	* testsuite/20_util/unique_ptr/lwg4148.cc: Likewise.
+ 	* testsuite/29_atomics/atomic/operators/pointer_partial_void.cc:
+ 	Likewise.
+ 	* testsuite/30_threads/packaged_task/cons/dangling_ref.cc:
+ 	Likewise.
+ 
  2025-09-12  Jonathan Wakely  <jwakely@redhat.com>
  
  	Backported from master:
diff -Nrcpad gcc-15-20250913/libstdc++-v3/testsuite/20_util/bind/dangling_ref.cc gcc-15-20250920/libstdc++-v3/testsuite/20_util/bind/dangling_ref.cc
*** gcc-15-20250913/libstdc++-v3/testsuite/20_util/bind/dangling_ref.cc	Sat Sep 13 22:32:57 2025
--- gcc-15-20250920/libstdc++-v3/testsuite/20_util/bind/dangling_ref.cc	Sat Sep 20 22:33:46 2025
***************
*** 1,4 ****
--- 1,5 ----
  // { dg-do compile { target c++11 } }
+ // { dg-additional-options "-Wsystem-headers" }
  #include <functional>
  
  int f();
diff -Nrcpad gcc-15-20250913/libstdc++-v3/testsuite/20_util/ratio/operations/ops_overflow_neg.cc gcc-15-20250920/libstdc++-v3/testsuite/20_util/ratio/operations/ops_overflow_neg.cc
*** gcc-15-20250913/libstdc++-v3/testsuite/20_util/ratio/operations/ops_overflow_neg.cc	Sat Sep 13 22:32:58 2025
--- gcc-15-20250920/libstdc++-v3/testsuite/20_util/ratio/operations/ops_overflow_neg.cc	Sat Sep 20 22:33:46 2025
***************
*** 1,6 ****
  // { dg-do compile { target c++11 } }
  // { dg-require-cstdint "" }
! 
  // 2008-07-03 Chris Fairles <chris.fairles@gmail.com>
  
  // Copyright (C) 2008-2025 Free Software Foundation, Inc.
--- 1,6 ----
  // { dg-do compile { target c++11 } }
  // { dg-require-cstdint "" }
! // { dg-additional-options "-Wsystem-headers" }
  // 2008-07-03 Chris Fairles <chris.fairles@gmail.com>
  
  // Copyright (C) 2008-2025 Free Software Foundation, Inc.
diff -Nrcpad gcc-15-20250913/libstdc++-v3/testsuite/20_util/unique_ptr/lwg4148.cc gcc-15-20250920/libstdc++-v3/testsuite/20_util/unique_ptr/lwg4148.cc
*** gcc-15-20250913/libstdc++-v3/testsuite/20_util/unique_ptr/lwg4148.cc	Sat Sep 13 22:32:58 2025
--- gcc-15-20250920/libstdc++-v3/testsuite/20_util/unique_ptr/lwg4148.cc	Sat Sep 20 22:33:46 2025
***************
*** 1,4 ****
--- 1,5 ----
  // { dg-do compile { target c++11 } }
+ // { dg-additional-options "-Wsystem-headers" }
  
  // LWG 4148. unique_ptr::operator* should not allow dangling references
  
diff -Nrcpad gcc-15-20250913/libstdc++-v3/testsuite/29_atomics/atomic/operators/pointer_partial_void.cc gcc-15-20250920/libstdc++-v3/testsuite/29_atomics/atomic/operators/pointer_partial_void.cc
*** gcc-15-20250913/libstdc++-v3/testsuite/29_atomics/atomic/operators/pointer_partial_void.cc	Sat Sep 13 22:33:02 2025
--- gcc-15-20250920/libstdc++-v3/testsuite/29_atomics/atomic/operators/pointer_partial_void.cc	Sat Sep 20 22:33:48 2025
***************
*** 1,6 ****
--- 1,7 ----
  // { dg-do run { target { c++11_only || c++14_only } } }
  // { dg-require-atomic-builtins "" }
  // { dg-require-effective-target hosted }
+ // { dg-additional-options "-Wsystem-headers" }
  
  // Copyright (C) 2012-2025 Free Software Foundation, Inc.
  //
diff -Nrcpad gcc-15-20250913/libstdc++-v3/testsuite/30_threads/packaged_task/cons/dangling_ref.cc gcc-15-20250920/libstdc++-v3/testsuite/30_threads/packaged_task/cons/dangling_ref.cc
*** gcc-15-20250913/libstdc++-v3/testsuite/30_threads/packaged_task/cons/dangling_ref.cc	Sat Sep 13 22:33:02 2025
--- gcc-15-20250920/libstdc++-v3/testsuite/30_threads/packaged_task/cons/dangling_ref.cc	Sat Sep 20 22:33:49 2025
***************
*** 1,4 ****
--- 1,5 ----
  // { dg-do compile { target c++11 } }
+ // { dg-additional-options "-Wsystem-headers" }
  #include <future>
  
  // C++20 [futures.task.members]
