diff -Nrcpad gcc-15-20251004/LAST_UPDATED gcc-15-20251011/LAST_UPDATED
*** gcc-15-20251004/LAST_UPDATED	Sat Oct  4 22:34:38 2025
--- gcc-15-20251011/LAST_UPDATED	Sat Oct 11 22:35:12 2025
***************
*** 1 ****
! Obtained from git: releases/gcc-15 revision 7ec702536bb759f4b1cc848d5a7670ab01edc90d
--- 1 ----
! Obtained from git: releases/gcc-15 revision c8acafb9e86a06bca8384e247168ce9a8599ded1
diff -Nrcpad gcc-15-20251004/MD5SUMS gcc-15-20251011/MD5SUMS
*** gcc-15-20251004/MD5SUMS	Sat Oct  4 22:34:43 2025
--- gcc-15-20251011/MD5SUMS	Sat Oct 11 22:35:18 2025
***************
*** 1,5 ****
  # This file contains the MD5 checksums of the files in the
! # gcc-15-20251004.tar.xz tarball.
  #
  # Besides verifying that all files in the tarball were correctly expanded,
  # it also can be used to determine if any files have changed since the
--- 1,5 ----
  # This file contains the MD5 checksums of the files in the
! # gcc-15-20251011.tar.xz tarball.
  #
  # Besides verifying that all files in the tarball were correctly expanded,
  # it also can be used to determine if any files have changed since the
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*** 3772,3778 ****
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*************** cc4d538f7d66895b427db54b9660a953  gcc/co
*** 4937,4943 ****
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--- 4937,4943 ----
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*************** f51037a9e437f8e9ce7215b2da5ad4e2  gcc/co
*** 4956,4962 ****
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*************** b1497a03867668af210c32280876fdd7  gcc/sy
*** 8446,8452 ****
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*************** a1131491d67160098e775860b91e3021  gcc/te
*** 72895,72902 ****
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*************** b61291f78078147f21c923a3c8b81a63  gcc/te
*** 72944,72949 ****
--- 72948,72955 ----
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*************** cbd676b663043514bbc26a8a6c3b7a9d  gcc/te
*** 72981,72986 ****
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*************** f0df0c8f4daf66789854622391d700cf  gcc/te
*** 73072,73077 ****
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*************** cf801f2e1c669d164d4ceb3cd657f647  gcc/te
*** 89539,89544 ****
--- 89547,89553 ----
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*************** c6f64767aa5c25a649dd1df61e9fbd20  gcc/te
*** 90835,90841 ****
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*************** fde5d5ed0c271572ac7da0e31e22bc5c  gcc/te
*** 112210,112215 ****
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  50be8d98f4f9ac99d64926a10596a2df  gcc/testsuite/gnat.dg/ref_type.adb
  5457827e708b7bfc92ffe5610655a443  gcc/testsuite/gnat.dg/ref_type.ads
  222b5d10f23a2e8e8a5e4d41e86e66ed  gcc/testsuite/gnat.dg/regpat1.adb
*************** b38cbc5c54988720ae33d36a2ff78fd3  libgcc
*** 118893,118912 ****
  5ab16e6eec7523296afc7c8bfee38565  libgcc/config/avr/lib1funcs.S
  622f81485f02d0eac2caaafa7d3a2fd1  libgcc/config/avr/lib2-object.mk
  e6604d88f15777c25f5d887ca1f9148c  libgcc/config/avr/lib2funcs.c
! 7ea0bb5e33f184a9e54a72e3c121a20d  libgcc/config/avr/libf7/ChangeLog
  dd74908d3b47db38a7aaa2e9f130f20f  libgcc/config/avr/libf7/asm-defs.h
! a5efc328f8686b92830ca73ea0b4d047  libgcc/config/avr/libf7/f7-renames.h
! 9bc93ce2b7213ad3cabff898a2d31774  libgcc/config/avr/libf7/f7-wraps.h
  b9901623ec29c1c4dd98d6fae040518c  libgcc/config/avr/libf7/f7renames.sh
  76d89fdf12c2153d7cf3d12c025a8713  libgcc/config/avr/libf7/f7wraps.sh
  b77774db3e278767f77ced55b8e1fe89  libgcc/config/avr/libf7/libf7-array.def
  5d9def53110ec07e8f29e66d593d758f  libgcc/config/avr/libf7/libf7-asm-object.mk
! ec9b30a882ac6a7401555a33253eb439  libgcc/config/avr/libf7/libf7-asm.sx
  6b4886ae302fca1fa733831066c5c830  libgcc/config/avr/libf7/libf7-c-object.mk
! 8c31d45420a77d0121484bfbb4e9304c  libgcc/config/avr/libf7/libf7-common.mk
  29f415bcdf1f8cf82363009ed90158a0  libgcc/config/avr/libf7/libf7-const.def
  4be27333f32f04990c0af746c07ffd5d  libgcc/config/avr/libf7/libf7-constdef.h
! ec9773d81bd91f723677eed83c9e9e33  libgcc/config/avr/libf7/libf7.c
  96bca6a7335f821140d30c203401c36e  libgcc/config/avr/libf7/libf7.h
  2921a86fef727ada45668b8c0f091e33  libgcc/config/avr/libf7/t-libf7
  bf9360cfc14e0b0129af5560893f374e  libgcc/config/avr/libf7/t-libf7-math
--- 118903,118922 ----
  5ab16e6eec7523296afc7c8bfee38565  libgcc/config/avr/lib1funcs.S
  622f81485f02d0eac2caaafa7d3a2fd1  libgcc/config/avr/lib2-object.mk
  e6604d88f15777c25f5d887ca1f9148c  libgcc/config/avr/lib2funcs.c
! 2e72c221c65b3afd34c07d0b1cff2632  libgcc/config/avr/libf7/ChangeLog
  dd74908d3b47db38a7aaa2e9f130f20f  libgcc/config/avr/libf7/asm-defs.h
! bd9ea3adc1ea81e3d0d05dc1b9999851  libgcc/config/avr/libf7/f7-renames.h
! fa695d06eee1fb3d5f9c3d904977f010  libgcc/config/avr/libf7/f7-wraps.h
  b9901623ec29c1c4dd98d6fae040518c  libgcc/config/avr/libf7/f7renames.sh
  76d89fdf12c2153d7cf3d12c025a8713  libgcc/config/avr/libf7/f7wraps.sh
  b77774db3e278767f77ced55b8e1fe89  libgcc/config/avr/libf7/libf7-array.def
  5d9def53110ec07e8f29e66d593d758f  libgcc/config/avr/libf7/libf7-asm-object.mk
! 686811c5649722c7336bf05e27415ddb  libgcc/config/avr/libf7/libf7-asm.sx
  6b4886ae302fca1fa733831066c5c830  libgcc/config/avr/libf7/libf7-c-object.mk
! 021ea561bcc2bc07286c89e312af685b  libgcc/config/avr/libf7/libf7-common.mk
  29f415bcdf1f8cf82363009ed90158a0  libgcc/config/avr/libf7/libf7-const.def
  4be27333f32f04990c0af746c07ffd5d  libgcc/config/avr/libf7/libf7-constdef.h
! 884b2f039045789cdd28e526e5587424  libgcc/config/avr/libf7/libf7.c
  96bca6a7335f821140d30c203401c36e  libgcc/config/avr/libf7/libf7.h
  2921a86fef727ada45668b8c0f091e33  libgcc/config/avr/libf7/t-libf7
  bf9360cfc14e0b0129af5560893f374e  libgcc/config/avr/libf7/t-libf7-math
diff -Nrcpad gcc-15-20251004/gcc/ChangeLog gcc-15-20251011/gcc/ChangeLog
*** gcc-15-20251004/gcc/ChangeLog	Sat Oct  4 22:32:28 2025
--- gcc-15-20251011/gcc/ChangeLog	Sat Oct 11 22:33:10 2025
***************
*** 1,3 ****
--- 1,70 ----
+ 2025-10-08  Aurelien Jarno  <aurelien@aurel32.net>
+ 
+ 	Backported from master:
+ 	2025-10-02  Aurelien Jarno  <aurelien@aurel32.net>
+ 
+ 	PR target/121652
+ 	* config/riscv/riscv.md (round_pattern): special case NaN input
+ 	instead of saving/restoring fflags.
+ 
+ 2025-10-07  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	Backported from master:
+ 	2025-10-07  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	PR target/122187
+ 	* config/avr/avr.cc (avr_out_extr, avr_out_extr_not):
+ 	Make a local copy of the passed rtx[] operands.
+ 
+ 2025-10-03  Robin Dapp  <rdapp@ventanamicro.com>
+ 
+ 	Backported from master:
+ 	2025-09-04  Robin Dapp  <rdapp@ventanamicro.com>
+ 
+ 	PR target/121742
+ 	PR target/121780
+ 	PR target/121781
+ 	* config/riscv/riscv-v.cc (expand_vec_perm): Swap target and
+ 	tmp_target.
+ 
+ 2025-10-03  Robin Dapp  <rdapp@ventanamicro.com>
+ 
+ 	Backported from master:
+ 	2025-09-02  Robin Dapp  <rdapp@ventanamicro.com>
+ 
+ 	PR target/121742
+ 	* config/riscv/riscv-v.cc (expand_vec_perm): Use temporary if
+ 	op1 and target overlap.
+ 
+ 2025-10-02  Kito Cheng  <kito.cheng@sifive.com>
+ 
+ 	PR target/110812
+ 	* config/riscv/riscv-c.cc (pragma_intrinsic_flags): Remove struct.
+ 	(riscv_pragma_intrinsic_flags_pollute): Remove function.
+ 	(riscv_pragma_intrinsic_flags_restore): Remove function.
+ 	(riscv_pragma_intrinsic): Simplify to only call handle_pragma_vector.
+ 	* config/riscv/riscv-vector-builtins.cc (pragma_intrinsic_flags):
+ 	Move struct definition here from riscv-c.cc.
+ 	(riscv_pragma_intrinsic_flags_pollute): Move and adapt from
+ 	riscv-c.cc, add zvfbfmin, zvfhmin and vector_elen_bf_16 support.
+ 	(riscv_pragma_intrinsic_flags_restore): Move from riscv-c.cc.
+ 	(rvv_switcher::rvv_switcher): Add pollute_flags parameter to
+ 	control flag manipulation.
+ 	(rvv_switcher::~rvv_switcher): Restore flags conditionally.
+ 	(register_builtin_types): Use rvv_switcher without polluting flags.
+ 	(get_required_extensions): Remove function.
+ 	(check_required_extensions): Simplify to only check type validity.
+ 	(function_instance::function_returns_void_p): Move implementation
+ 	from header.
+ 	(function_builder::add_function): Register placeholder for LTO.
+ 	(init_builtins): Simplify and handle LTO case.
+ 	(reinit_builtins): Remove function.
+ 	(handle_pragma_vector): Remove extension checking.
+ 	* config/riscv/riscv-vector-builtins.h
+ 	(function_instance::function_returns_void_p): Add declaration.
+ 	(function_call_info::function_returns_void_p): Remove inline
+ 	implementation.
+ 
  2025-09-26  Lulu Cheng  <chenglulu@loongson.cn>
  
  	Backported from master:
diff -Nrcpad gcc-15-20251004/gcc/DATESTAMP gcc-15-20251011/gcc/DATESTAMP
*** gcc-15-20251004/gcc/DATESTAMP	Sat Oct  4 22:32:28 2025
--- gcc-15-20251011/gcc/DATESTAMP	Sat Oct 11 22:33:11 2025
***************
*** 1 ****
! 20251002
--- 1 ----
! 20251011
diff -Nrcpad gcc-15-20251004/gcc/ada/ChangeLog gcc-15-20251011/gcc/ada/ChangeLog
*** gcc-15-20251004/gcc/ada/ChangeLog	Sat Oct  4 22:32:28 2025
--- gcc-15-20251011/gcc/ada/ChangeLog	Sat Oct 11 22:33:11 2025
***************
*** 1,3 ****
--- 1,8 ----
+ 2025-10-05  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	PR ada/118343
+ 	* Makefile.rtl (LLVM_BUILD): Delete.
+ 
  2025-09-30  Eric Botcazou  <ebotcazou@adacore.com>
  
  	PR ada/117517
diff -Nrcpad gcc-15-20251004/gcc/ada/Makefile.rtl gcc-15-20251011/gcc/ada/Makefile.rtl
*** gcc-15-20251004/gcc/ada/Makefile.rtl	Sat Oct  4 22:32:28 2025
--- gcc-15-20251011/gcc/ada/Makefile.rtl	Sat Oct 11 22:33:11 2025
*************** ifndef ADAC
*** 26,37 ****
  ADAC=$(CC)
  endif
  
- ifeq ($(LLVM_CONFIG),)
- LLVM_BUILD := $(shell $(ADAC) -v | grep ^llvm-gcc)
- else
- LLVM_BUILD := llvm-gcc
- endif
- 
  # Objects needed only for tasking
  GNATRTL_TASKING_OBJS= \
    a-dispat$(objext) \
--- 26,31 ----
diff -Nrcpad gcc-15-20251004/gcc/config/avr/avr.cc gcc-15-20251011/gcc/config/avr/avr.cc
*** gcc-15-20251004/gcc/config/avr/avr.cc	Sat Oct  4 22:32:36 2025
--- gcc-15-20251011/gcc/config/avr/avr.cc	Sat Oct 11 22:33:13 2025
*************** avr_out_insv (rtx_insn *insn, rtx xop[],
*** 10212,10227 ****
  }
  
  
! /* Output instructions to extract a bit to 8-bit register XOP[0].
!    The input XOP[1] is a register or an 8-bit MEM in the lower I/O range.
!    XOP[2] is the const_int bit position.  Return "".
  
     PLEN != 0: Set *PLEN to the code length in words.  Don't output anything.
     PLEN == 0: Output instructions.  */
  
  const char *
! avr_out_extr (rtx_insn *insn, rtx xop[], int *plen)
  {
    rtx dest = xop[0];
    rtx src = xop[1];
    int bit = INTVAL (xop[2]);
--- 10212,10228 ----
  }
  
  
! /* Output instructions to extract a bit to 8-bit register OP[0].
!    The input OP[1] is a register or an 8-bit MEM in the lower I/O range.
!    OP[2] is the const_int bit position.  Return "".
  
     PLEN != 0: Set *PLEN to the code length in words.  Don't output anything.
     PLEN == 0: Output instructions.  */
  
  const char *
! avr_out_extr (rtx_insn *insn, rtx op[], int *plen)
  {
+   rtx xop[] = { op[0], op[1], op[2] };
    rtx dest = xop[0];
    rtx src = xop[1];
    int bit = INTVAL (xop[2]);
*************** avr_out_extr (rtx_insn *insn, rtx xop[],
*** 10279,10294 ****
  }
  
  
! /* Output instructions to extract a negated bit to 8-bit register XOP[0].
!    The input XOP[1] is an 8-bit register or MEM in the lower I/O range.
!    XOP[2] is the const_int bit position.  Return "".
  
     PLEN != 0: Set *PLEN to the code length in words.  Don't output anything.
     PLEN == 0: Output instructions.  */
  
  const char *
! avr_out_extr_not (rtx_insn * /* insn */, rtx xop[], int *plen)
  {
    rtx dest = xop[0];
    rtx src = xop[1];
    int bit = INTVAL (xop[2]);
--- 10280,10296 ----
  }
  
  
! /* Output instructions to extract a negated bit to 8-bit register OP[0].
!    The input OP[1] is an 8-bit register or MEM in the lower I/O range.
!    OP[2] is the const_int bit position.  Return "".
  
     PLEN != 0: Set *PLEN to the code length in words.  Don't output anything.
     PLEN == 0: Output instructions.  */
  
  const char *
! avr_out_extr_not (rtx_insn * /* insn */, rtx op[], int *plen)
  {
+   rtx xop[] = { op[0], op[1], op[2] };
    rtx dest = xop[0];
    rtx src = xop[1];
    int bit = INTVAL (xop[2]);
diff -Nrcpad gcc-15-20251004/gcc/config/riscv/riscv-v.cc gcc-15-20251011/gcc/config/riscv/riscv-v.cc
*** gcc-15-20251004/gcc/config/riscv/riscv-v.cc	Sat Oct  4 22:32:39 2025
--- gcc-15-20251011/gcc/config/riscv/riscv-v.cc	Sat Oct 11 22:33:14 2025
*************** shuffle_series_patterns (struct expand_v
*** 3946,3951 ****
--- 3946,3954 ----
    bool need_insert = false;
    bool have_series = false;
  
+   poly_int64 len = d->perm.length ();
+   bool need_modulo = !len.is_constant ();
+ 
    /* Check for a full series.  */
    if (known_ne (step1, 0) && d->perm.series_p (0, 1, el1, step1))
      have_series = true;
*************** shuffle_series_patterns (struct expand_v
*** 3957,3963 ****
        need_insert = true;
      }
  
!   if (!have_series)
      return false;
  
    /* Disable shuffle if we can't find an appropriate integer index mode for
--- 3960,3992 ----
        need_insert = true;
      }
  
!   /* A permute like {0, 3, 2, 1} is recognized as series because series_p also
!      allows wrapping/modulo of the permute index.  The step would be 3 and the
!      indices are correct modulo 4.  As noted in expand_vec_perm vrgather does
!      not handle wrapping but rather zeros out-of-bounds indices.
!      This means we would need to emit an explicit modulo operation here which
!      does not seem worth it.  We rather defer to the generic handling instead.
!      Even in the non-wrapping case it is doubtful whether
!       vid
!       vmul
!       vrgather
!      is preferable over
!       vle
!       vrgather.
!      If the permute mask can be reused there shouldn't be any difference and
!      otherwise it becomes a question of load bandwidth.  */
!   if (have_series && len.is_constant ())
!     {
!       int64_t step = need_insert ? step2.to_constant () : step1.to_constant ();
!       int prec = GET_MODE_PRECISION (GET_MODE_INNER (d->vmode));
!       wide_int wlen = wide_int::from (len.to_constant (), prec * 2, SIGNED);
!       wide_int wstep = wide_int::from (step, prec * 2, SIGNED);
!       wide_int result = wi::mul (wlen, wstep);
!       if (wi::gt_p (result, wlen, SIGNED))
! 	need_modulo = true;
!     }
! 
!   if (!have_series || (len.is_constant () && need_modulo))
      return false;
  
    /* Disable shuffle if we can't find an appropriate integer index mode for
*************** shuffle_series_patterns (struct expand_v
*** 3976,3981 ****
--- 4005,4017 ----
    expand_vec_series (series, gen_int_mode (need_insert ? el2 : el1, eltmode),
  		     gen_int_mode (need_insert ? step2 : step1, eltmode));
  
+   if (need_modulo)
+     {
+       rtx mod = gen_const_vector_dup (sel_mode, len - 1);
+       series = expand_simple_binop (sel_mode, AND, series, mod, NULL,
+ 				    0, OPTAB_DIRECT);
+     }
+ 
    /* Insert the remaining element if necessary.  */
    if (need_insert)
      {
diff -Nrcpad gcc-15-20251004/gcc/config/riscv/riscv.md gcc-15-20251011/gcc/config/riscv/riscv.md
*** gcc-15-20251004/gcc/config/riscv/riscv.md	Sat Oct  4 22:32:39 2025
--- gcc-15-20251011/gcc/config/riscv/riscv.md	Sat Oct 11 22:33:14 2025
***************
*** 2281,2307 ****
    else
      {
        rtx reg;
!       rtx label = gen_label_rtx ();
        rtx end_label = gen_label_rtx ();
        rtx abs_reg = gen_reg_rtx (<ANYF:MODE>mode);
        rtx coeff_reg = gen_reg_rtx (<ANYF:MODE>mode);
        rtx tmp_reg = gen_reg_rtx (<ANYF:MODE>mode);
-       rtx fflags = gen_reg_rtx (SImode);
  
        riscv_emit_move (tmp_reg, operands[1]);
        riscv_emit_move (coeff_reg,
  		       riscv_vector::get_fp_rounding_coefficient (<ANYF:MODE>mode));
        emit_insn (gen_abs<ANYF:mode>2 (abs_reg, operands[1]));
  
!       /* fp compare can set invalid flag for NaN, so backup fflags.  */
!       if (flag_trapping_math)
!         emit_insn (gen_riscv_frflags (fflags));
!       riscv_expand_conditional_branch (label, LT, abs_reg, coeff_reg);
  
        emit_jump_insn (gen_jump (end_label));
        emit_barrier ();
  
!       emit_label (label);
        switch (<ANYF:MODE>mode)
  	{
  	case SFmode:
--- 2281,2318 ----
    else
      {
        rtx reg;
!       rtx label1 = gen_label_rtx ();
!       rtx label2 = gen_label_rtx ();
!       rtx label3 = gen_label_rtx ();
        rtx end_label = gen_label_rtx ();
        rtx abs_reg = gen_reg_rtx (<ANYF:MODE>mode);
        rtx coeff_reg = gen_reg_rtx (<ANYF:MODE>mode);
        rtx tmp_reg = gen_reg_rtx (<ANYF:MODE>mode);
  
        riscv_emit_move (tmp_reg, operands[1]);
+ 
+       if (flag_trapping_math)
+ 	{
+ 	  /* Check if the input is a NaN.  */
+ 	  riscv_expand_conditional_branch (label1, EQ,
+ 					   operands[1], operands[1]);
+ 
+ 	  emit_jump_insn (gen_jump (label3));
+ 	  emit_barrier ();
+ 
+ 	  emit_label (label1);
+ 	}
+ 
        riscv_emit_move (coeff_reg,
  		       riscv_vector::get_fp_rounding_coefficient (<ANYF:MODE>mode));
        emit_insn (gen_abs<ANYF:mode>2 (abs_reg, operands[1]));
  
!       riscv_expand_conditional_branch (label2, LT, abs_reg, coeff_reg);
  
        emit_jump_insn (gen_jump (end_label));
        emit_barrier ();
  
!       emit_label (label2);
        switch (<ANYF:MODE>mode)
  	{
  	case SFmode:
***************
*** 2320,2334 ****
  
        emit_insn (gen_copysign<ANYF:mode>3 (tmp_reg, abs_reg, operands[1]));
  
!       emit_label (end_label);
  
-       /* Restore fflags, but after label.  This is slightly different
-          than glibc implementation which only needs to restore under
-          the label, since it checks for NaN first, meaning following fp
-          compare can't raise fp exceptons and thus not clobber fflags.  */
        if (flag_trapping_math)
!         emit_insn (gen_riscv_fsflags (fflags));
  
        riscv_emit_move (operands[0], tmp_reg);
      }
  
--- 2331,2347 ----
  
        emit_insn (gen_copysign<ANYF:mode>3 (tmp_reg, abs_reg, operands[1]));
  
!       emit_jump_insn (gen_jump (end_label));
!       emit_barrier ();
  
        if (flag_trapping_math)
! 	{
! 	  emit_label (label3);
! 	  /* Generate a qNaN from an sNaN if needed.  */
! 	  emit_insn (gen_add<ANYF:mode>3 (tmp_reg, operands[1], operands[1]));
! 	}
  
+       emit_label (end_label);
        riscv_emit_move (operands[0], tmp_reg);
      }
  
diff -Nrcpad gcc-15-20251004/gcc/testsuite/ChangeLog gcc-15-20251011/gcc/testsuite/ChangeLog
*** gcc-15-20251004/gcc/testsuite/ChangeLog	Sat Oct  4 22:32:44 2025
--- gcc-15-20251011/gcc/testsuite/ChangeLog	Sat Oct 11 22:33:17 2025
***************
*** 1,3 ****
--- 1,106 ----
+ 2025-10-09  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	Backported from master:
+ 	2025-10-09  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	PR target/122222
+ 	* gcc.target/avr/pr122222-sitod.c: New test.
+ 
+ 2025-10-09  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	Backported from master:
+ 	2025-10-09  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	PR target/122220
+ 	* gcc.target/avr/pr122220.c: New test.
+ 
+ 2025-10-09  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	Backported from master:
+ 	2025-10-09  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	PR target/122210
+ 	* gcc.target/avr/dtofx.c: New test.
+ 
+ 2025-10-09  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	Backported from master:
+ 	2025-10-09  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	PR target/122210
+ 	* gcc.target/avr/fxtod.c: New test.
+ 
+ 2025-10-08  Aurelien Jarno  <aurelien@aurel32.net>
+ 
+ 	Backported from master:
+ 	2025-10-02  Aurelien Jarno  <aurelien@aurel32.net>
+ 
+ 	PR target/121652
+ 	* gcc.target/riscv/rvv/autovec/vls/math-nearbyint-1.c: Adjust
+ 	scan pattern for fewer instances of frflags/fsrflags.
+ 
+ 2025-10-07  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	Backported from master:
+ 	2025-10-07  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	PR target/122187
+ 	* gcc.target/avr/torture/pr122187.c: New test.
+ 
+ 2025-10-06  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	Backported from master:
+ 	2025-10-06  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	* gcc.target/avr/sincos-1.c: New test.
+ 
+ 2025-10-06  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	Backported from master:
+ 	2025-10-06  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	PR target/122177
+ 	* gcc.target/avr/fminfmax-1.c: New test.
+ 
+ 2025-10-06  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	Backported from master:
+ 	2025-10-06  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	* gcc.target/avr/cmpdi-1.c: New test.
+ 
+ 2025-10-05  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	PR ada/113536
+ 	* gnat.dg/reduce2.adb: New test.
+ 
+ 2025-10-03  Robin Dapp  <rdapp@ventanamicro.com>
+ 
+ 	Backported from master:
+ 	2025-09-04  Robin Dapp  <rdapp@ventanamicro.com>
+ 
+ 	PR target/121742
+ 	PR target/121780
+ 	PR target/121781
+ 	* gcc.target/riscv/rvv/autovec/pr121780.c: New test.
+ 	* gcc.target/riscv/rvv/autovec/pr121781.c: New test.
+ 
+ 2025-10-03  Robin Dapp  <rdapp@ventanamicro.com>
+ 
+ 	Backported from master:
+ 	2025-09-02  Robin Dapp  <rdapp@ventanamicro.com>
+ 
+ 	PR target/121742
+ 	* gcc.target/riscv/rvv/autovec/pr121742.c: New test.
+ 
+ 2025-10-02  Kito Cheng  <kito.cheng@sifive.com>
+ 
+ 	PR target/110812
+ 	* gcc.target/riscv/lto/pr110812_0.c: New test.
+ 	* gcc.target/riscv/lto/pr110812_1.c: New test.
+ 	* gcc.target/riscv/lto/riscv-lto.exp: New test driver.
+ 	* gcc.target/riscv/lto/riscv_vector.h: New header wrapper.
+ 
  2025-09-30  Eric Botcazou  <ebotcazou@adacore.com>
  
  	* gnat.dg/reduce1.adb: New test.
diff -Nrcpad gcc-15-20251004/gcc/testsuite/gcc.target/avr/cmpdi-1.c gcc-15-20251011/gcc/testsuite/gcc.target/avr/cmpdi-1.c
*** gcc-15-20251004/gcc/testsuite/gcc.target/avr/cmpdi-1.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20251011/gcc/testsuite/gcc.target/avr/cmpdi-1.c	Sat Oct 11 22:34:15 2025
***************
*** 0 ****
--- 1,149 ----
+ /* { dg-do run { target { ! avr_tiny } } } */
+ /* { dg-additional-options { -std=gnu99 -Os -mcall-prologues } } */
+ 
+ typedef __INT8_TYPE__   int8_t;
+ typedef __UINT8_TYPE__  uint8_t;
+ typedef __UINT16_TYPE__ uint16_t;
+ typedef __UINT64_TYPE__ uint64_t;
+ typedef __INT64_TYPE__  int64_t;
+ 
+ #define ARRAY_SIZE(X) (sizeof(X) / sizeof(*X))
+ 
+ const __flash uint64_t mant[] =
+   {
+     0x0000000000000,
+     0x0000000000001,
+     0x0000000000100,
+     0x0000000010000,
+     0x0000001000000,
+     0x0000100000000,
+     0x0010000000000,
+     0x1000000000000,
+     0x00000000000ff,
+     0x00000000000ff,
+     0x000000000ffff,
+     0x0000000ffffff,
+     0x00000ffffffff,
+     0x000ffffffffff,
+     0x0ffffffffffff,
+     0xfffffffffffff,
+     0xfffffffffff00,
+     0xfffffffff0000,
+     0xfffffff000000,
+     0xfffff00000000,
+     0xfff0000000000,
+     0xff00000000000,
+     0xf000000000000,
+     0x7ffffffffffff,
+     0x8000000000000,
+     0x8000000000001,
+     0xffffffffffffe
+   };
+ 
+ const __flash uint16_t expo[] =
+   {
+     0x000,
+     0x001,
+     0x002,
+     0x7fe,
+     0x7ff
+   };
+ 
+ #define SMASK ((uint64_t) 1 << 63)
+ #define xNAN 0x7f
+ 
+ char d64_nan_p (uint64_t a)
+ {
+   return (a & ~SMASK) > (uint64_t) 0x7ff << 52;
+ }
+ 
+ int8_t cmp_d64 (uint64_t a, uint64_t b)
+ {
+   if (d64_nan_p (a) || d64_nan_p (b))
+     return xNAN;
+ 
+   if (a & SMASK)     a = SMASK - a;
+   if (b & SMASK)     b = SMASK - b;
+   __asm ("" : "+r" (a));
+   __asm ("" : "+r" (b));
+ 
+   return a == b
+     ? 0
+     : (int64_t) a > (int64_t) b ? 1 : -1;
+ }
+ 
+ extern int8_t eq (uint64_t, uint64_t) __asm("__eqdf2");
+ extern int8_t ne (uint64_t, uint64_t) __asm("__nedf2");
+ extern int8_t ge (uint64_t, uint64_t) __asm("__gedf2");
+ extern int8_t gt (uint64_t, uint64_t) __asm("__gtdf2");
+ extern int8_t le (uint64_t, uint64_t) __asm("__ledf2");
+ extern int8_t lt (uint64_t, uint64_t) __asm("__ltdf2");
+ extern int8_t unord (uint64_t, uint64_t) __asm("__unorddf2");
+ 
+ void test1 (uint64_t a, uint64_t b)
+ {
+   int8_t d, c = cmp_d64 (a, b);
+   d = eq (a, b);
+   if (c == xNAN && d) __builtin_exit (1);
+   if (c != xNAN && d != (c == 0)) __builtin_exit (2);
+ 
+   d = ne (a, b);
+   if (c == xNAN && d) __builtin_exit (3);
+   if (c != xNAN && d != (c != 0)) __builtin_exit (4);
+ 
+   d = ge (a, b);
+   if (c == xNAN && d) __builtin_exit (5);
+   if (c != xNAN && d != (c >= 0)) __builtin_exit (6);
+ 
+   d = gt (a, b);
+   if (c == xNAN && d) __builtin_exit (7);
+   if (c != xNAN && d != (c > 0)) __builtin_exit (8);
+ 
+   d = le (a, b);
+   if (c == xNAN && d) __builtin_exit (9);
+   if (c != xNAN && d != (c <= 0)) __builtin_exit (10);
+ 
+   d = lt (a, b);
+   if (c == xNAN && d) __builtin_exit (11);
+   if (c != xNAN && d != (c < 0)) __builtin_exit (12);
+ 
+   d = unord (a, b);
+   if (c == xNAN && !d) __builtin_exit (13);
+   if (c != xNAN && d) __builtin_exit (14);
+ }
+ 
+ 
+ void testAB (uint64_t a, uint64_t b)
+ {
+   test1 (a, b);
+   test1 (a, b ^ SMASK);
+   test1 (a ^ SMASK, b);
+   test1 (a ^ SMASK, b ^ SMASK);
+ }
+ 
+ void testA (uint64_t a)
+ {
+   for (uint8_t i = 0; i < ARRAY_SIZE (mant); ++i)
+     {
+       uint64_t b = mant[i];
+       for (uint8_t j = 0; j < ARRAY_SIZE (expo); ++j)
+ 	testAB (a, b | ((uint64_t) expo[j] << 52));
+     }
+ }
+ 
+ void tests (void)
+ {
+   for (uint8_t i = 0; i < ARRAY_SIZE (mant); ++i)
+     {
+       uint64_t a = mant[i];
+       for (uint8_t j = 0; j < ARRAY_SIZE (expo); ++j)
+ 	testA (a | ((uint64_t) expo[j] << 52));
+     }
+ }
+ 
+ 
+ int main (void)
+ {
+   tests ();
+   return 0;
+ }
diff -Nrcpad gcc-15-20251004/gcc/testsuite/gcc.target/avr/dtofx.c gcc-15-20251011/gcc/testsuite/gcc.target/avr/dtofx.c
*** gcc-15-20251004/gcc/testsuite/gcc.target/avr/dtofx.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20251011/gcc/testsuite/gcc.target/avr/dtofx.c	Sat Oct 11 22:34:15 2025
***************
*** 0 ****
--- 1,98 ----
+ /* { dg-do run { target { ! avr_tiny } } } */
+ /* { dg-additional-options { -std=gnu99 -Os -mcall-prologues -Wno-pedantic } } */
+ 
+ #include <stdfix.h>
+ 
+ #if __SIZEOF_LONG_DOUBLE__ == 8
+ 
+ typedef long double D;
+ 
+ volatile D d0 = 0;
+ volatile D dm15 = -1.5;
+ volatile D dp15 = +1.5;
+ volatile D dm05 = -0.5;
+ volatile D dp05 = +0.5;
+ 
+ void test0 (void)
+ {
+   if (0hk != (short accum) d0)
+     __builtin_exit (__LINE__);
+ 
+   if (0uhk != (unsigned short accum) d0)
+     __builtin_exit (__LINE__);
+ 
+   if (0hr != (short fract) d0)
+     __builtin_exit (__LINE__);
+ 
+   if (0uhr != (unsigned short fract) d0)
+     __builtin_exit (__LINE__);
+ 
+   if (0k != (accum) d0)
+     __builtin_exit (__LINE__);
+ 
+   if (0uk != (unsigned accum) d0)
+     __builtin_exit (__LINE__);
+ 
+   if (0r != (fract) d0)
+     __builtin_exit (__LINE__);
+ 
+   if (0ur != (unsigned fract) d0)
+     __builtin_exit (__LINE__);
+ }
+ 
+ void testp (void)
+ {
+   if (0.5hr != (short fract) dp05)
+     __builtin_exit (__LINE__);
+ 
+   if (0.5uhr != (unsigned short fract) dp05)
+     __builtin_exit (__LINE__);
+ 
+   if (0.5r != (fract) dp05)
+     __builtin_exit (__LINE__);
+ 
+   if (0.5ur != (unsigned fract) dp05)
+     __builtin_exit (__LINE__);
+ 
+   if (1.5hk != (short accum) dp15)
+     __builtin_exit (__LINE__);
+ 
+   if (1.5uhk != (unsigned short accum) dp15)
+     __builtin_exit (__LINE__);
+ 
+   if (1.5k != (accum) dp15)
+     __builtin_exit (__LINE__);
+ 
+   if (1.5uk != (unsigned accum) dp15)
+     __builtin_exit (__LINE__);
+ }
+ 
+ void testm (void)
+ {
+   if (-0.5hr != (short fract) dm05)
+     __builtin_exit (__LINE__);
+ 
+   if (-0.5r != (fract) dm05)
+     __builtin_exit (__LINE__);
+ 
+   if (-1.5hk != (short accum) dm15)
+     __builtin_exit (__LINE__);
+ 
+   if (-1.5k != (accum) dm15)
+     __builtin_exit (__LINE__);
+ }
+ 
+ int main (void)
+ {
+   test0 ();
+   testp ();
+   testm ();
+ 
+   return 0;
+ }
+ #else
+ int main (void)
+ {
+   return 0;
+ }
+ #endif
diff -Nrcpad gcc-15-20251004/gcc/testsuite/gcc.target/avr/fminfmax-1.c gcc-15-20251011/gcc/testsuite/gcc.target/avr/fminfmax-1.c
*** gcc-15-20251004/gcc/testsuite/gcc.target/avr/fminfmax-1.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20251011/gcc/testsuite/gcc.target/avr/fminfmax-1.c	Sat Oct 11 22:34:15 2025
***************
*** 0 ****
--- 1,116 ----
+ /* { dg-do run { target { ! avr_tiny } } } */
+ /* { dg-additional-options { -std=gnu99 -Os -mcall-prologues } } */
+ 
+ typedef __INT8_TYPE__   int8_t;
+ typedef __UINT8_TYPE__  uint8_t;
+ typedef __UINT16_TYPE__ uint16_t;
+ typedef __UINT64_TYPE__ uint64_t;
+ typedef __INT64_TYPE__  int64_t;
+ 
+ #define ARRAY_SIZE(X) (sizeof(X) / sizeof(*X))
+ 
+ const __flash uint64_t vals[] =
+   {
+     // NaNs
+     0xffffffffffffffff,
+     0x7fffffffffffffff,
+     0xfff0000000000001,
+     0x7ff0000000000001,
+ 
+     // Some non-NaN doubles, increasing in magnitude.
+     0xfff0000000000000, // -Inf
+     0xffefffffffffffff,
+     0xffe0000000000000,
+     0x8010000000000000,
+     0x800fffffffffffff,
+     0x800ffffffffffffe,
+     0x8007fffffffffffe,
+     0x8000000000000001,
+     0x0000000000000000,
+     0x0000000000000001,
+     0x0007fffffffffffe,
+     0x000ffffffffffffe,
+     0x000fffffffffffff,
+     0x0010000000000000,
+     0x7fe0000000000000,
+     0x7fefffffffffffff,
+     0x7ff0000000000000  // +Inf
+   };
+ 
+ #define SMASK ((uint64_t) 1 << 63)
+ 
+ char d64_nan_p (uint64_t a)
+ {
+   return (a & ~SMASK) > (uint64_t) 0x7ff << 52;
+ }
+ 
+ extern uint64_t xmin (uint64_t, uint64_t) __asm("__fmin");
+ extern uint64_t xmax (uint64_t, uint64_t) __asm("__fmax");
+ 
+ void test_fmin (uint8_t i, uint8_t j)
+ {
+   uint64_t a = vals[i];
+   uint64_t b = vals[j];
+   uint64_t m = xmin (a, b);
+ 
+   char a_nan_p = d64_nan_p (a);
+   char b_nan_p = d64_nan_p (b);
+ 
+   if (a_nan_p + b_nan_p == 2)
+     {
+       if (!d64_nan_p (m))
+ 	__builtin_exit (__LINE__);
+     }
+   else
+     {
+       uint64_t r = 0?0
+ 	: a_nan_p ? b
+ 	: b_nan_p ? a
+ 	: i < j ? a : b;
+       if (r != m)
+ 	__builtin_exit (__LINE__);
+     }
+ }
+ 
+ 
+ void test_fmax (uint8_t i, uint8_t j)
+ {
+   uint64_t a = vals[i];
+   uint64_t b = vals[j];
+   uint64_t m = xmax (a, b);
+ 
+   char a_nan_p = d64_nan_p (a);
+   char b_nan_p = d64_nan_p (b);
+ 
+   if (a_nan_p + b_nan_p == 2)
+     {
+       if (!d64_nan_p (m))
+ 	__builtin_exit (__LINE__);
+     }
+   else
+     {
+       uint64_t r = 0?0
+ 	: a_nan_p ? b
+ 	: b_nan_p ? a
+ 	: i > j ? a : b;
+       if (r != m)
+ 	__builtin_exit (__LINE__);
+     }
+ }
+ 
+ 
+ void tests (void)
+ {
+   for (uint8_t i = 0; i < ARRAY_SIZE (vals); ++i)
+     for (uint8_t j = 0; j < ARRAY_SIZE (vals); ++j)
+       {
+ 	test_fmin (i, j);
+       }
+ }
+ 
+ 
+ int main (void)
+ {
+   tests ();
+   return 0;
+ }
diff -Nrcpad gcc-15-20251004/gcc/testsuite/gcc.target/avr/fxtod.c gcc-15-20251011/gcc/testsuite/gcc.target/avr/fxtod.c
*** gcc-15-20251004/gcc/testsuite/gcc.target/avr/fxtod.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20251011/gcc/testsuite/gcc.target/avr/fxtod.c	Sat Oct 11 22:34:15 2025
***************
*** 0 ****
--- 1,115 ----
+ /* { dg-do run { target { ! avr_tiny } } } */
+ /* { dg-additional-options { -std=gnu99 -Os -mcall-prologues -fwrapv -Wno-overflow } } */
+ 
+ #include <stdfix.h>
+ 
+ #if __SIZEOF_LONG_DOUBLE__ == 8
+ 
+ #define NI __attribute__((noipa))
+ 
+ typedef long double D;
+ 
+ extern D ldexpl (D, int);
+ 
+ typedef short fract hr_t;
+ typedef unsigned short fract uhr_t;
+ typedef fract r_t;
+ typedef unsigned fract ur_t;
+ 
+ typedef short accum hk_t;
+ typedef unsigned short accum uhk_t;
+ typedef accum k_t;
+ typedef unsigned accum uk_t;
+ 
+ #define FBITuhr 8
+ #define FBIThr  7
+ #define FBITur  16
+ #define FBITr   15
+ 
+ #define FBITuhk 8
+ #define FBIThk  7
+ #define FBITuk  16
+ #define FBITk   15
+ 
+ #define VALff(S) ((2ul << (8 * sizeof (S##bits(0)) - 1)) - 1)
+ #define VAL80(S) (1ul << (8 * sizeof (S##bits(0)) - 1))
+ #define VAL00(S) 0
+ #define VAL01(S) 1
+ 
+ 
+ #define TEST_U(S, V)				\
+   NI void test_##S##_##V (void)			\
+   {						\
+     S##_t x = S##bits (VAL##V (S));		\
+     __asm ("" : "+r" (x));			\
+     D d = (D) x;				\
+     D z = ldexpl (VAL##V (S), - FBIT##S);	\
+     if (d != z)					\
+       __builtin_exit (1);			\
+   }
+ 
+ #define TEST_S(S, V)				\
+   NI void test_##S##_##V (void)			\
+   {						\
+     uint32_t u32 = (VAL##V (S) & VAL80 (S))	\
+       ? 1u + (VAL##V (S) ^ VALff (S))		\
+       : VAL##V (S);				\
+     S##_t x = S##bits (VAL##V (S));		\
+     __asm ("" : "+r" (x));			\
+     D d = (D) x;				\
+     D z = ldexpl (u32, - FBIT##S);		\
+     int s = (VAL##V (S) & VAL80 (S)) != 0;	\
+     if (s == 0 && d != z)			\
+       __builtin_exit (2);			\
+     if (s == 1 && d != -z)			\
+       __builtin_exit (3);			\
+   }
+ 
+ #define TESTS_U(S)				\
+   TEST_U (S, 00)				\
+   TEST_U (S, 01)				\
+   TEST_U (S, ff)				\
+   TEST_U (S, 80)
+ 
+ #define TESTS_S(S)				\
+   TEST_S (S, 00)				\
+   TEST_S (S, 01)				\
+   TEST_S (S, ff)				\
+   TEST_S (S, 80)
+ 
+ TESTS_U (uhr)
+ TESTS_U (ur)
+ TESTS_U (uhk)
+ TESTS_U (uk)
+ 
+ TESTS_S (hr)
+ TESTS_S (r)
+ TESTS_S (hk)
+ TESTS_S (k)
+ 
+ #define RUN(S)		\
+   test_##S##_00 ();	\
+   test_##S##_01 ();	\
+   test_##S##_ff ();	\
+   test_##S##_80 ()
+   
+ int main (void)
+ {
+   RUN (uhr);
+   RUN (ur);
+   RUN (uhk);
+   RUN (uk);
+ 
+   RUN (hr);
+   RUN (r);
+   RUN (hk);
+   RUN (k);
+ 
+   return 0;
+ }
+ #else
+ int main (void)
+ {
+   return 0;
+ }
+ #endif
diff -Nrcpad gcc-15-20251004/gcc/testsuite/gcc.target/avr/pr122220.c gcc-15-20251011/gcc/testsuite/gcc.target/avr/pr122220.c
*** gcc-15-20251004/gcc/testsuite/gcc.target/avr/pr122220.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20251011/gcc/testsuite/gcc.target/avr/pr122220.c	Sat Oct 11 22:34:15 2025
***************
*** 0 ****
--- 1,23 ----
+ /* { dg-do run { target { ! avr_tiny } } } */
+ /* { dg-additional-options { -std=gnu99 -Os -mcall-prologues } } */
+ 
+ #if __SIZEOF_LONG_DOUBLE__ == 8
+ 
+ typedef long double D;
+ typedef __INT32_TYPE__ int32_t;
+ 
+ D dd = -0x1p31L;
+   
+ int main (void)
+ {
+   if ((int32_t) dd != -0x7fffffff - 1)
+     __builtin_abort();
+ 
+   return 0;
+ }
+ #else
+ int main (void)
+ {
+   return 0;
+ }
+ #endif
diff -Nrcpad gcc-15-20251004/gcc/testsuite/gcc.target/avr/pr122222-sitod.c gcc-15-20251011/gcc/testsuite/gcc.target/avr/pr122222-sitod.c
*** gcc-15-20251004/gcc/testsuite/gcc.target/avr/pr122222-sitod.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20251011/gcc/testsuite/gcc.target/avr/pr122222-sitod.c	Sat Oct 11 22:34:15 2025
***************
*** 0 ****
--- 1,60 ----
+ /* { dg-do run { target { ! avr_tiny } } } */
+ /* { dg-additional-options { -std=gnu99 -Os -mcall-prologues } } */
+ 
+ #if __SIZEOF_LONG_DOUBLE__ == 8
+ 
+ typedef long double D;
+ typedef __INT32_TYPE__  int32_t;
+ typedef __UINT32_TYPE__ uint32_t;
+ typedef __UINT8_TYPE__  uint8_t;
+ 
+ #define ARRAY_SIZE(X) (sizeof(X) / sizeof(*X))
+ 
+ void testu (void)
+ {
+   static const volatile __flash uint32_t vals[] =
+     {
+       0, 1ul, -1ul, (-1ul) << 1,
+       1ul << 31, 1ul << 30, 1ul << 29, 1ul << 28, 1ul << 27, 1ul << 26,
+       1ul << 25, 1ul << 24, 0xff, 123456789
+     };
+ 
+   for (uint8_t i = 0; i < ARRAY_SIZE (vals); ++i)
+     {
+       D x = (D) vals[i];
+       __asm ("" : "+r" (x));
+       if ((uint32_t) x != vals[i])
+ 	__builtin_exit (__LINE__);
+     }
+ }
+ 
+ void tests (void)
+ {
+   static const volatile __flash int32_t vals[] =
+     {
+       0, 1L, -1L, 0x7fffffff, -0x7fffffff, -0x7fffffff - 1,
+       -123456789
+     };
+ 
+   for (uint8_t i = 0; i < ARRAY_SIZE (vals); ++i)
+     {
+       D x = (D) vals[i];
+       __asm ("" : "+r" (x));
+       if ((int32_t) x != vals[i])
+ 	__builtin_exit (__LINE__);
+     }
+ }
+ 
+ int main (void)
+ {
+   testu ();
+   tests ();
+ 
+   return 0;
+ }
+ #else
+ int main (void)
+ {
+   return 0;
+ }
+ #endif
diff -Nrcpad gcc-15-20251004/gcc/testsuite/gcc.target/avr/sincos-1.c gcc-15-20251011/gcc/testsuite/gcc.target/avr/sincos-1.c
*** gcc-15-20251004/gcc/testsuite/gcc.target/avr/sincos-1.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20251011/gcc/testsuite/gcc.target/avr/sincos-1.c	Sat Oct 11 22:34:15 2025
***************
*** 0 ****
--- 1,35 ----
+ /* { dg-do run { target { ! avr_tiny } } } */
+ /* { dg-additional-options { -std=gnu99 -Os -mcall-prologues } } */
+ 
+ #if __SIZEOF_LONG_DOUBLE__ == 8
+ typedef long double D;
+ 
+ extern void sincosl (D, D*, D*);
+ extern D sinl (D);
+ extern D cosl (D);
+ 
+ D s1, c1;
+ 
+ int main (void)
+ {
+   for (D x = -20; x < 20; x += 1.1)
+     {
+       sincosl (x, &s1, &c1);
+ 
+       __asm ("" : "+r" (x) :: "memory");
+ 
+       if (s1 != sinl (x))
+ 	__builtin_exit (1);
+ 
+       if (c1 != cosl (x))
+ 	__builtin_exit (2);
+     }
+ 
+   return 0;
+ }
+ #else
+ int main (void)
+ {
+   return 0;
+ }
+ #endif
diff -Nrcpad gcc-15-20251004/gcc/testsuite/gcc.target/avr/torture/pr122187.c gcc-15-20251011/gcc/testsuite/gcc.target/avr/torture/pr122187.c
*** gcc-15-20251004/gcc/testsuite/gcc.target/avr/torture/pr122187.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20251011/gcc/testsuite/gcc.target/avr/torture/pr122187.c	Sat Oct 11 22:34:15 2025
***************
*** 0 ****
--- 1,17 ----
+ /* { dg-do compile } */
+ /* { dg-additional-options { -std=c99 } } */
+ 
+ typedef __UINT32_TYPE__ uint32_t;
+ typedef __UINT16_TYPE__ uint16_t;
+ typedef __UINT8_TYPE__ uint8_t;
+ 
+ #define PINB (*(volatile uint8_t*) (13 + __AVR_SFR_OFFSET__))
+ #define PB1 1
+ 
+ uint16_t fun (void)
+ {
+     uint16_t h = 0;
+     for (uint32_t s = 0; s < 0x10000; ++s)
+         h += (PINB >> PB1) & 1;
+     return h;
+ }
diff -Nrcpad gcc-15-20251004/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr121845.c gcc-15-20251011/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr121845.c
*** gcc-15-20251004/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr121845.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20251011/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr121845.c	Sat Oct 11 22:34:21 2025
***************
*** 0 ****
--- 1,37 ----
+ /* { dg-do run } */
+ /* { dg-require-effective-target riscv_v_ok } */
+ /* { dg-options "-march=rv64gcv -mabi=lp64d -O0" } */
+ 
+ #include <stdint.h>
+ typedef uint32_t a;
+ typedef uint64_t uint64;
+ 
+ uint64 b;
+ __attribute__ ((__vector_size__ (4 * sizeof (a)))) a f = {504339, 7, 3};
+ uint64 *g = &b;
+ 
+ int32_t *
+ c (uint8_t, int32_t *, uint32_t, uint32_t, int64_t);
+ int8_t
+ d ()
+ {
+   int32_t e;
+   c (0, &e, 0, 0, 1);
+   return 0;
+ }
+ 
+ int32_t *
+ c (uint8_t, int32_t *j, uint32_t, uint32_t, int64_t)
+ {
+   f = __builtin_shufflevector (f, f, 0, 3, 2, 1);
+   *g = f[2];
+   return j;
+ }
+ 
+ int
+ main ()
+ {
+   d ();
+   if (b != 3)
+     __builtin_abort ();
+ }
diff -Nrcpad gcc-15-20251004/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-nearbyint-1.c gcc-15-20251011/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-nearbyint-1.c
*** gcc-15-20251004/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-nearbyint-1.c	Sat Oct  4 22:33:44 2025
--- gcc-15-20251011/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-nearbyint-1.c	Sat Oct 11 22:34:25 2025
*************** DEF_OP_V (nearbyint, 512, double, __buil
*** 54,58 ****
  /* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
  /* { dg-final { scan-assembler-times {vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t} 30 } } */
  /* { dg-final { scan-assembler-times {vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t} 30 } } */
! /* { dg-final { scan-assembler-times {frflags\s+[atx][0-9]+} 32 } } */
! /* { dg-final { scan-assembler-times {fsflags\s+[atx][0-9]+} 32 } } */
--- 54,58 ----
  /* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
  /* { dg-final { scan-assembler-times {vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t} 30 } } */
  /* { dg-final { scan-assembler-times {vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t} 30 } } */
! /* { dg-final { scan-assembler-times {frflags\s+[atx][0-9]+} 30 } } */
! /* { dg-final { scan-assembler-times {fsflags\s+[atx][0-9]+} 30 } } */
diff -Nrcpad gcc-15-20251004/gcc/testsuite/gnat.dg/reduce2.adb gcc-15-20251011/gcc/testsuite/gnat.dg/reduce2.adb
*** gcc-15-20251004/gcc/testsuite/gnat.dg/reduce2.adb	Thu Jan  1 00:00:00 1970
--- gcc-15-20251011/gcc/testsuite/gnat.dg/reduce2.adb	Sat Oct 11 22:34:36 2025
***************
*** 0 ****
--- 1,18 ----
+ -- { dg-do compile }
+ -- { dg-options "-gnat2022" }
+ 
+ procedure Reduce2 is
+ 
+   subtype Value is Natural range 0 .. 255;
+ 
+   function Do_Something (Accumulator : Value; Symbol : Character) return Value
+     is (((Accumulator + Character'Pos (Symbol)) * 17) mod 256);
+ 
+   function Do_It_By_Reduction (S : String) return Value is
+     (S'Reduce (Do_Something, 0));
+ 
+   Test_It : constant Value := Do_It_By_Reduction ("Hello, world!");
+ 
+ begin
+   null;
+ end;
diff -Nrcpad gcc-15-20251004/libgcc/config/avr/libf7/ChangeLog gcc-15-20251011/libgcc/config/avr/libf7/ChangeLog
*** gcc-15-20251004/libgcc/config/avr/libf7/ChangeLog	Sat Oct  4 22:34:05 2025
--- gcc-15-20251011/libgcc/config/avr/libf7/ChangeLog	Sat Oct 11 22:34:38 2025
***************
*** 1,3 ****
--- 1,73 ----
+ 2025-10-09  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	Backported from master:
+ 	2025-10-09  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	PR target/122222
+ 	* libf7-asm.sx (D_floatsidf, D_floatunsidf): New modules.
+ 	* libf7-common.mk (F7_ASM_PARTS): Add D_floatsidf, D_floatunsidf.
+ 	(F7F, g_dx): Remove floatunsidf, floatsidf.
+ 	* libf7.c (f7_set_s32): Don't alias to f7_floatsidf.
+ 	(f7_set_u32): Don't alias to f7_floatunsidf.
+ 	* f7-renames.h: Rebuild
+ 	* f7-wraps.h: Rebuild.
+ 
+ 2025-10-09  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	Backported from master:
+ 	2025-10-09  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	PR target/122220
+ 	* libf7-asm.sx (to_integer): Return 0x80... on negative overflow.
+ 
+ 2025-10-09  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	Backported from master:
+ 	2025-10-09  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	PR target/122210
+ 	* libf7-common.mk (F7_ASM_PARTS): Add D2<fx> modules.
+ 	* libf7-asm.sx: Implement the D2<fx> modules.
+ 
+ 2025-10-09  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	Backported from master:
+ 	2025-10-09  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	PR target/122210
+ 	* libf7-common.mk (F7_ASM_PARTS): Add <fx>2D modules.
+ 	* libf7-asm.sx: Implement the <fx>2D modules.
+ 
+ 2025-10-06  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	Backported from master:
+ 	2025-10-06  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	* libf7-common.mk (F7_ASM_PARTS): Add D_sincos.
+ 	* libf7-asm.sx: (D_sincos): New module implements sincos / sincosl.
+ 
+ 2025-10-06  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	Backported from master:
+ 	2025-10-06  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	PR target/122177
+ 	* libf7-common.mk (m_ddd): Remove: fmin, fmax.
+ 	(F7_ASM_PARTS): Add: D_fminfmax.
+ 	* libf7-asm.sx (D_fmanfmax): New module.
+ 	* f7-wraps.h: Rebuild.
+ 
+ 2025-10-06  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	Backported from master:
+ 	2025-10-06  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	* libf7-common.mk (g_xdd_cmp): Remove le, lt, ge, gt, ne, eq, unord.
+ 	(F7_ASM_PARTS): Add D_cmp, D_eq, D_ne, D_ge, D_gt, D_le, D_lt, D_unord.
+ 	* libf7-asm.sx (D_cmp, D_eq, D_ne, D_ge, D_gt, D_le, D_lt, D_unord):
+ 	New modules.
+ 	* f7-wraps.h: Rebuild.
+ 
  2025-08-08  Release Manager
  
  	* GCC 15.2.0 released.
diff -Nrcpad gcc-15-20251004/libgcc/config/avr/libf7/f7-renames.h gcc-15-20251011/libgcc/config/avr/libf7/f7-renames.h
*** gcc-15-20251004/libgcc/config/avr/libf7/f7-renames.h	Sat Oct  4 22:34:05 2025
--- gcc-15-20251011/libgcc/config/avr/libf7/f7-renames.h	Sat Oct 11 22:34:38 2025
***************
*** 159,166 ****
  #define f7_min __f7_min
  #define f7_max __f7_max
  #define f7_exp10 __f7_exp10
- #define f7_floatunsidf __f7_floatunsidf
- #define f7_floatsidf __f7_floatsidf
  #define f7_extendsfdf2 __f7_extendsfdf2
  #define f7_fixdfsi __f7_fixdfsi
  #define f7_fixdfdi __f7_fixdfdi
--- 159,164 ----
diff -Nrcpad gcc-15-20251004/libgcc/config/avr/libf7/f7-wraps.h gcc-15-20251011/libgcc/config/avr/libf7/f7-wraps.h
*** gcc-15-20251004/libgcc/config/avr/libf7/f7-wraps.h	Sat Oct  4 22:34:05 2025
--- gcc-15-20251011/libgcc/config/avr/libf7/f7-wraps.h	Sat Oct 11 22:34:38 2025
*************** _ENDF __divdf3
*** 79,155 ****
  #endif /* F7MOD_D_div_ */
  
  ;; Functions that usually live in libgcc: __<name>df2 for <name> in:
! ;; le lt ge gt ne eq unord
! 
! ;; bool __ledf2 (double, double)  ; le
! #ifdef F7MOD_D_le_
! _DEFUN __ledf2
!     .global F7_NAME(le_impl)
!     ldi     ZH,     hi8(gs(F7_NAME(le_impl)))
!     ldi     ZL,     lo8(gs(F7_NAME(le_impl)))
!     F7jmp   call_xdd
! _ENDF __ledf2
! #endif /* F7MOD_D_le_ */
! 
! ;; bool __ltdf2 (double, double)  ; lt
! #ifdef F7MOD_D_lt_
! _DEFUN __ltdf2
!     .global F7_NAME(lt_impl)
!     ldi     ZH,     hi8(gs(F7_NAME(lt_impl)))
!     ldi     ZL,     lo8(gs(F7_NAME(lt_impl)))
!     F7jmp   call_xdd
! _ENDF __ltdf2
! #endif /* F7MOD_D_lt_ */
! 
! ;; bool __gedf2 (double, double)  ; ge
! #ifdef F7MOD_D_ge_
! _DEFUN __gedf2
!     .global F7_NAME(ge_impl)
!     ldi     ZH,     hi8(gs(F7_NAME(ge_impl)))
!     ldi     ZL,     lo8(gs(F7_NAME(ge_impl)))
!     F7jmp   call_xdd
! _ENDF __gedf2
! #endif /* F7MOD_D_ge_ */
! 
! ;; bool __gtdf2 (double, double)  ; gt
! #ifdef F7MOD_D_gt_
! _DEFUN __gtdf2
!     .global F7_NAME(gt_impl)
!     ldi     ZH,     hi8(gs(F7_NAME(gt_impl)))
!     ldi     ZL,     lo8(gs(F7_NAME(gt_impl)))
!     F7jmp   call_xdd
! _ENDF __gtdf2
! #endif /* F7MOD_D_gt_ */
! 
! ;; bool __nedf2 (double, double)  ; ne
! #ifdef F7MOD_D_ne_
! _DEFUN __nedf2
!     .global F7_NAME(ne_impl)
!     ldi     ZH,     hi8(gs(F7_NAME(ne_impl)))
!     ldi     ZL,     lo8(gs(F7_NAME(ne_impl)))
!     F7jmp   call_xdd
! _ENDF __nedf2
! #endif /* F7MOD_D_ne_ */
! 
! ;; bool __eqdf2 (double, double)  ; eq
! #ifdef F7MOD_D_eq_
! _DEFUN __eqdf2
!     .global F7_NAME(eq_impl)
!     ldi     ZH,     hi8(gs(F7_NAME(eq_impl)))
!     ldi     ZL,     lo8(gs(F7_NAME(eq_impl)))
!     F7jmp   call_xdd
! _ENDF __eqdf2
! #endif /* F7MOD_D_eq_ */
! 
! ;; bool __unorddf2 (double, double)  ; unord
! #ifdef F7MOD_D_unord_
! _DEFUN __unorddf2
!     .global F7_NAME(unord_impl)
!     ldi     ZH,     hi8(gs(F7_NAME(unord_impl)))
!     ldi     ZL,     lo8(gs(F7_NAME(unord_impl)))
!     F7jmp   call_xdd
! _ENDF __unorddf2
! #endif /* F7MOD_D_unord_ */
  
  ;; Functions that usually live in libgcc: __<name> for <name> in:
  ;; fixdfsi fixdfdi fixunsdfdi fixunsdfsi truncdfsf2
--- 79,85 ----
  #endif /* F7MOD_D_div_ */
  
  ;; Functions that usually live in libgcc: __<name>df2 for <name> in:
! ;; (none)
  
  ;; Functions that usually live in libgcc: __<name> for <name> in:
  ;; fixdfsi fixdfdi fixunsdfdi fixunsdfsi truncdfsf2
*************** _ENDF __truncdfsf2
*** 205,231 ****
  #endif /* F7MOD_D_truncdfsf2_ */
  
  ;; Functions that usually live in libgcc: __<name> for <name> in:
! ;; floatunsidf floatsidf extendsfdf2
! 
! ;; double __floatunsidf (type_t)  ; floatunsidf
! #ifdef F7MOD_D_floatunsidf_
! _DEFUN __floatunsidf
!     .global F7_NAME(floatunsidf)
!     ldi     ZH,     hi8(gs(F7_NAME(floatunsidf)))
!     ldi     ZL,     lo8(gs(F7_NAME(floatunsidf)))
!     F7jmp   call_dx
! _ENDF __floatunsidf
! #endif /* F7MOD_D_floatunsidf_ */
! 
! ;; double __floatsidf (type_t)  ; floatsidf
! #ifdef F7MOD_D_floatsidf_
! _DEFUN __floatsidf
!     .global F7_NAME(floatsidf)
!     ldi     ZH,     hi8(gs(F7_NAME(floatsidf)))
!     ldi     ZL,     lo8(gs(F7_NAME(floatsidf)))
!     F7jmp   call_dx
! _ENDF __floatsidf
! #endif /* F7MOD_D_floatsidf_ */
  
  ;; double __extendsfdf2 (type_t)  ; extendsfdf2
  #ifdef F7MOD_D_extendsfdf2_
--- 135,141 ----
  #endif /* F7MOD_D_truncdfsf2_ */
  
  ;; Functions that usually live in libgcc: __<name> for <name> in:
! ;; extendsfdf2
  
  ;; double __extendsfdf2 (type_t)  ; extendsfdf2
  #ifdef F7MOD_D_extendsfdf2_
*************** _ENDF __extendsfdf2
*** 239,245 ****
  
  ;; Functions that usually live in libm:  Depending on [long] double layout,
  ;; define <name> and <name>l as weak alias(es) of __<name> for <name> in:
! ;; pow fmin fmax fmod hypot atan2 fdim
  
  ;; double __pow (double, double)
  #ifdef F7MOD_D_pow_
--- 149,155 ----
  
  ;; Functions that usually live in libm:  Depending on [long] double layout,
  ;; define <name> and <name>l as weak alias(es) of __<name> for <name> in:
! ;; pow fmod hypot atan2 fdim
  
  ;; double __pow (double, double)
  #ifdef F7MOD_D_pow_
*************** _DEFUN __pow
*** 253,282 ****
  _ENDF __pow
  #endif /* F7MOD_D_pow_ */
  
- ;; double __fmin (double, double)
- #ifdef F7MOD_D_fmin_
- _DEFUN __fmin
-     DALIAS fmin
-     LALIAS fminl
-     .global F7_NAME(fmin)
-     ldi     ZH,     hi8(gs(F7_NAME(fmin)))
-     ldi     ZL,     lo8(gs(F7_NAME(fmin)))
-     F7jmp   call_ddd
- _ENDF __fmin
- #endif /* F7MOD_D_fmin_ */
- 
- ;; double __fmax (double, double)
- #ifdef F7MOD_D_fmax_
- _DEFUN __fmax
-     DALIAS fmax
-     LALIAS fmaxl
-     .global F7_NAME(fmax)
-     ldi     ZH,     hi8(gs(F7_NAME(fmax)))
-     ldi     ZL,     lo8(gs(F7_NAME(fmax)))
-     F7jmp   call_ddd
- _ENDF __fmax
- #endif /* F7MOD_D_fmax_ */
- 
  ;; double __fmod (double, double)
  #ifdef F7MOD_D_fmod_
  _DEFUN __fmod
--- 163,168 ----
diff -Nrcpad gcc-15-20251004/libgcc/config/avr/libf7/libf7-asm.sx gcc-15-20251011/libgcc/config/avr/libf7/libf7-asm.sx
*** gcc-15-20251004/libgcc/config/avr/libf7/libf7-asm.sx	Sat Oct  4 22:34:05 2025
--- gcc-15-20251011/libgcc/config/avr/libf7/libf7-asm.sx	Sat Oct 11 22:34:38 2025
*************** DEFUN to_integer
*** 618,638 ****
  .Lsaturate.T:
  
  #if F7_HAVE_Inf
!     brtc .Lset_0x7fff
!     ;; -Inf  =>  return 1 + INTxx_MIN
!     mov     ZL,     Flags
!     .global __clr_8
!     XCALL   __clr_8
!     ldi     C6,     0x80
! 
!     ldi     CA+0,   0x01
! 
!     sbrs    Mask,   5
!     ldi     CA+4,   0x01
! 
!     sbrs    Mask,   4
!     ldi     CA+6,   0x01
!     ret
  
  .Lset_0x7fff:
      ;; +Inf  =>  return INTxx_MAX
--- 618,624 ----
  .Lsaturate.T:
  
  #if F7_HAVE_Inf
!     brts .Lset_0x8000
  
  .Lset_0x7fff:
      ;; +Inf  =>  return INTxx_MAX
*************** DEFUN to_integer
*** 644,650 ****
  #endif /* F7_HAVE_Inf */
  
  .Lset_0x8000:
!     ;; NaN  =>  return INTxx_MIN
      .global __clr_8
      XCALL   __clr_8
      ldi     C6,     0x80
--- 630,636 ----
  #endif /* F7_HAVE_Inf */
  
  .Lset_0x8000:
!     ;; NaN  or -Inf =>  return INTxx_MIN
      .global __clr_8
      XCALL   __clr_8
      ldi     C6,     0x80
*************** ENDF class_D
*** 1727,1732 ****
--- 1713,2033 ----
  #endif /* F7MOD_D_class_ */
  
  
+ #ifdef F7MOD_D_cmp_
+ 
+ #define A0  18
+ #define A1  A0 + 1
+ #define A2  A0 + 2
+ #define A3  A0 + 3
+ #define A4  A0 + 4
+ #define A5  A0 + 5
+ #define A6  A0 + 6
+ #define A7  A0 + 7
+ 
+ #define B0  10
+ #define B1  B0 + 1
+ #define B2  B0 + 2
+ #define B3  B0 + 3
+ #define B4  B0 + 4
+ #define B5  B0 + 5
+ #define B6  B0 + 6
+ #define B7  B0 + 7
+ 
+ #define AA5  XH
+ #define AA6  ZL
+ #define AA7  ZH
+ 
+ #define BB0  A0
+ #define BB1  A1
+ #define BB2  A2
+ #define BB3  A3
+ #define BB4  A4
+ #define BB5  A5
+ #define BB6  A6
+ #define BB7  A7
+ 
+ ;;; Helper for __<cmp>df2 and __unorddf2.
+ ;;; T = 1: Comparison is unordered.
+ ;;; T = 0: Comparison is ordered, and Z, N, C, S flags are set according
+ ;;; to compare (double A, double B) as if set by a signed int comparison.
+ ;;; Note that f(+0) = f(-0) = 0.
+ ;;; In any case:
+ ;;; -  return R24 = 1.
+ ;;; -  return R25.0 = isNaN (A)
+ ;;; -  return R25.1 = isNaN (B)
+ DEFUN D_cmp
+     rcall   D_cmp.map_i64
+     bld     __tmp_reg__, 0
+     push    __tmp_reg__
+     ;; Save A somewhere else...
+     wmov    AA6, A6
+     mov     AA5, A5
+     push    A4
+     push    A3
+     push    A2
+     push    A1
+     mov     r0,  A0
+     ;; ... so that we can use D_cmp.map_i64 on B.
+     wmov    BB6, B6
+     wmov    BB4, B4
+     wmov    BB2, B2
+     wmov    BB0, B0
+     rcall   D_cmp.map_i64
+     ;; Run the following code even when B is NaN (T=1) so as to pop the regs.
+     ;; In the non-NaN case, AA and BB can be compared like int64_t for the
+     ;; sake of comparing A and B as double.
+     CP      r0,  BB0  $  pop r0
+     cpc     r0,  BB1  $  pop r0
+     cpc     r0,  BB2  $  pop r0
+     cpc     r0,  BB3  $  pop r0
+     cpc     r0,  BB4
+     cpc     AA5, BB5
+     cpc     AA6, BB6
+     cpc     AA7, BB7
+     pop     r25
+     ;; R25.0 <=> A is NaN
+     ;; R25.1 <=> B is NaN
+     ;; T <=> comparison is unordered
+     bld     r25, 1
+     sbrc    r25, 0
+     set
+     ldi     r24, 1
+     ret
+ 
+ ;;; A is NaN: Set T=1.
+ ;;; A is not a NaN: Set T=0, and map double A to int64_t such that
+ ;;; f(A) <cmp> f(B)  iff  A <cmp> B, i.e. we can treat the result
+ ;;; as int64_t for the matter of double comparison.
+ ;;; Clobbers: XL.
+ D_cmp.map_i64:
+     bst     A7, 7
+     cbr     A7, 0x80
+     ;; If Inf < |A|, then we have a NaN.
+     CP      __zero_reg__, A0
+     cpc     __zero_reg__, A1
+     cpc     __zero_reg__, A2
+     cpc     __zero_reg__, A3
+     cpc     __zero_reg__, A4
+     cpc     __zero_reg__, A5
+     ldi     XL, lo8(0x7ff0)     $    cpc    XL, A6
+     ldi     XL, hi8(0x7ff0)     $    cpc    XL, A7
+     brlo .Lunord
+     brtc 9f
+     clt
+     .global __negdi2
+     XJMP    __negdi2
+ .Lunord:
+     set
+ 9:  ret
+ 
+ ENDF D_cmp
+ #endif /* F7MOD_D_cmp_ */
+ 
+ 
+ ;; bool __ledf2 (double, double);
+ #ifdef F7MOD_D_le_
+ _DEFUN __ledf2
+     F7call  D_cmp
+     brts 0f
+     breq 1f
+     brlt 1f
+ 0:  ldi     r24, 0
+ 1:  ret
+ _ENDF __ledf2
+ #endif /* F7MOD_D_le_ */
+ 
+ ;; bool __ltdf2 (double, double);
+ #ifdef F7MOD_D_lt_
+ _DEFUN __ltdf2
+     F7call  D_cmp
+     brts 0f
+     brlt 1f
+ 0:  ldi     r24, 0
+ 1:  ret
+ _ENDF __ltdf2
+ #endif /* F7MOD_D_lt_ */
+ 
+ ;; bool __gedf2 (double, double);
+ #ifdef F7MOD_D_ge_
+ _DEFUN __gedf2
+     F7call  D_cmp
+     brts 0f
+     brge 1f
+ 0:  ldi     r24, 0
+ 1:  ret
+ _ENDF __gedf2
+ #endif /* F7MOD_D_ge_ */
+ 
+ ;; bool __gtdf2 (double, double);
+ #ifdef F7MOD_D_gt_
+ _DEFUN __gtdf2
+     F7call  D_cmp
+     brts 0f
+     breq 0f
+     brge 1f
+ 0:  ldi     r24, 0
+ 1:  ret
+ _ENDF __gtdf2
+ #endif /* F7MOD_D_gt_ */
+ 
+ ;; bool __nedf2 (double, double);
+ #ifdef F7MOD_D_ne_
+ _DEFUN __nedf2
+     F7call  D_cmp
+     brts 0f
+     brne 1f
+ 0:  ldi     r24, 0
+ 1:  ret
+ _ENDF __nedf2
+ #endif /* F7MOD_D_ne_ */
+ 
+ ;; bool __eqdf2 (double, double);
+ #ifdef F7MOD_D_eq_
+ _DEFUN __eqdf2
+     F7call  D_cmp
+     brts 0f
+     breq 1f
+ 0:  ldi     r24, 0
+ 1:  ret
+ _ENDF __eqdf2
+ #endif /* F7MOD_D_eq_ */
+ 
+ ;; bool __unorddf2 (double, double);
+ #ifdef F7MOD_D_unord_
+ _DEFUN __unorddf2
+     F7call  D_cmp
+     bld     r24, 0
+     ret
+ _ENDF __unorddf2
+ #endif /* F7MOD_D_unord_ */
+ 
+ #ifdef F7MOD_D_fminfmax_
+ _DEFUN __fmin
+ DALIAS fmin
+ LALIAS fminl
+     inc     __zero_reg__
+ 
+ _LABEL __fmax
+ DALIAS fmax
+ LALIAS fmaxl
+     ;; Push A[].
+     push    r25
+     push    r24
+     push    r23
+     push    r22
+     push    r21
+     push    r20
+     push    r19
+     push    r18
+     ;; fmin or fmax
+     push    __zero_reg__
+     clr     __zero_reg__
+ 
+     XCALL   __gedf2
+ 
+     pop     __tmp_reg__
+     andi    r25, 0x3            ; NaNs?
+     brne .Lnan
+     ;; No NaNs involved.
+     eor     __tmp_reg__, r24    ; (f == fmin) ^ (A >= B)
+     brne 1f
+ 2:
+     ;; Return B since the cases are:
+     ;; fmax && A < B
+     ;; fmin && A >= B
+ #ifdef __AVR_XMEGA__
+     in      XL, __SP_L__
+     in      XH, __SP_H__
+     adiw    XL, 8
+     out     __SP_L__, XL
+     out     __SP_H__, XH
+ #else
+     pop r0  $  pop r0  $  pop r0  $  pop r0
+     pop r0  $  pop r0  $  pop r0  $  pop r0
+ #endif
+     wmov    r24, r16
+     wmov    r22, r14
+     wmov    r20, r12
+     wmov    r18, r10
+     ret
+ 1:
+     ;; Return A since the cases are:
+     ;; fmax && A >= B
+     ;; fmin && A < B
+     pop     r18
+     pop     r19
+     pop     r20
+     pop     r21
+     pop     r22
+     pop     r23
+     pop     r24
+     pop     r25
+     ret
+ 
+ .Lnan:
+     ;; There are NaNs.
+     ;; When only the 1st argument is a NaN, then return the 2nd argument
+     cpi     r25, 0x1
+     breq 2b
+     ;; When the 2nd argument is a NaN, then return the 1st argument.
+     ;; When both arguments are NaNs, then return NaN (e.g. the 1st argument).
+     rjmp 1b
+ _ENDF __fmax
+ #endif /* F7MOD_D_fminfmax_ */
+ 
+ 
+ #ifdef F7MOD_D_sincos_
+ ;;; void sincos (double R18, double *R16, double *R14);
+ _DEFUN __sincos
+ DALIAS sincos
+ LALIAS sincosl
+ 
+ #define n_pushed    4
+ #define n_frame    (2 * F7_SIZEOF)
+     do_prologue_saves n_pushed, n_frame
+     ;; Y = FramePointer + 1
+     adiw    Y,      1
+     ;; R16 = frame-arg 1
+     wmov    r16,    Y
+     ;; The double argument is in R18[].
+     XCALL   F7_NAME (set_double_impl)
+     ;; void f7_sincos (f7_t *ss, f7_t *cc, const f7_t *aa)
+     ;; Note that aa may equal ss or cc.
+     wmov    r20,    r16                 ; aa
+     wmov    r24,    r16                 ; ss = FP + 1
+     subi    r16,    lo8(-F7_SIZEOF)
+     sbci    r17,    hi8(-F7_SIZEOF)
+     wmov    r22,    r16                 ; cc = FP + 1 + F7_SIZEOF
+     XCALL   F7_NAME (sincos)
+ 
+     ;; double R18 = get_double (cc)
+     wmov    r24,    r16
+     XCALL   F7_NAME (get_double)
+     wmov    XL,     r14                 ; double *pcos
+     rcall   store.r18.X                 ; *pcos = R18
+ 
+     ;; double R18 = get_double (ss)
+     wmov    r24,    Y
+     XCALL   F7_NAME (get_double)
+     ldd     XL,     Y + n_frame + 3     ; Saved R16
+     ldd     XH,     Y + n_frame + 2     ; Saved R17
+     rcall   store.r18.X                 ; *psin = R18
+ 
+     do_epilogue_restores n_pushed, n_frame
+ 
+ store.r18.X:
+     st      X+,     r18
+     st      X+,     r19
+     st      X+,     r20
+     st      X+,     r21
+     st      X+,     r22
+     st      X+,     r23
+     st      X+,     r24
+     st      X+,     r25
+     ret
+ _ENDF __sincos
+ #endif /* F7MOD_D_sincos_ */
+ 
  #ifdef F7MOD_call_dd_
  
  ;; Provide double wrappers for functions that operate on f7_t and get f7_t*.
*************** _DEFUN __powidf2
*** 1894,1897 ****
--- 2195,2471 ----
  _ENDF __powidf2
  #endif /* F7MOD_D_powi_ */
  
+ 
+ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+ ;;; Fixed-point -> double conversions.
+ 
+ ;;; The double exponent starts at bit 52 since the encoded mantissa has 52 bits.
+ ;;; Note that when X is a multiple of 16, then dex_lo(x) evaluates to 0.
+ #define DEX16(x)  (x) << (52 - 48)
+ #define dex_lo(x) lo8 (DEX16 (x))
+ #define dex_hi(x) hi8 (DEX16 (x))
+ 
+ #ifdef F7MOD_usa2D_
+ _DEFUN __fractusadf
+     ;; Convert USI to DF.
+     XCALL   __floatunsidf
+     ;; The MSB indicates a value of 0.
+     cpse    r25, __zero_reg__
+     ;; Divide non-zero values by 2^16 in order to adjust for FBIT = 16.
+     subi    r25, dex_hi (16)
+     ret
+ _ENDF __fractusadf
+ #endif /* F7MOD_usa2D_ */
+ 
+ #ifdef F7MOD_sa2D_
+ _DEFUN __fractsadf
+     ;; Convert SI to DF.
+     XCALL   __floatsidf
+     ;; The MSB indicates a value of 0.
+     tst     r25
+     breq 0f
+     ;; Divide non-zero values by 2^15 in order to adjust for FBIT = 15.
+     subi    r24, dex_lo (15)
+     sbci    r25, dex_hi (15)
+ 0:  ret
+ _ENDF __fractsadf
+ #endif /* F7MOD_sa2D_ */
+ 
+ #ifdef F7MOD_uha2D_
+ _DEFUN __fractuhadf
+     ;; Extend UHA to USA.
+     clr     r22
+     mov     r23, r24
+     mov     r24, r25
+     clr     r25
+     XJMP    __fractusadf
+ _ENDF __fractuhadf
+ #endif /* F7MOD_uha2D_ */
+ 
+ #ifdef F7MOD_ha2D_
+ _DEFUN __fracthadf
+     ;; Extend HA to SA.
+     clr     r22
+     mov     r23, r24
+     mov     r24, r25
+     lsl     r25
+     sbc     r25, r25
+     XJMP    __fractsadf
+ _ENDF __fracthadf
+ #endif /* F7MOD_ha2D_ */
+ 
+ 
+ #ifdef F7MOD_usq2D_
+ _DEFUN __fractusqdf
+     ;; Convert USI to DF.
+     XCALL   __floatunsidf
+     ;; The MSB indicates a value of 0.
+     cpse    r25, __zero_reg__
+     ;; Divide non-zero values by 2^32 in order to adjust for FBIT = 32.
+     subi    r25, dex_hi (32)
+     ret
+ _ENDF __fractusqdf
+ #endif /* F7MOD_usq2D_ */
+ 
+ #ifdef F7MOD_sq2D_
+ _DEFUN __fractsqdf
+     ;; Convert SI to DF.
+     XCALL   __floatsidf
+     ;; The MSB indicates a value of 0.
+     tst     r25
+     breq 0f
+     ;; Divide non-zero values by 2^31 in order to adjust for FBIT = 31.
+     subi    r24, dex_lo (31)
+     sbci    r25, dex_hi (31)
+ 0:  ret
+ _ENDF __fractsqdf
+ #endif /* F7MOD_sq2D_ */
+ 
+ #ifdef F7MOD_uqq2D_
+ _DEFUN __fractuqqdf
+     ;; Extend UQQ to UHQ.
+     mov     r25, r24
+     clr     r24
+ _LABEL __fractuhqdf
+     ;; Extend UHQ to USQ.
+     clr     r23
+     clr     r22
+     XJMP    __fractusqdf
+ _ENDF __fractuqqdf
+ #endif /* F7MOD_uqq2D_ */
+ 
+ #ifdef F7MOD_qq2D_
+ _DEFUN __fractqqdf
+     ;; Extend QQ to HQ.
+     mov     r25, r24
+     clr     r24
+ _LABEL __fracthqdf
+     ;; Extend HQ to SQ.
+     clr     r23
+     clr     r22
+     XJMP    __fractsqdf
+ _ENDF __fractqqdf
+ #endif /* F7MOD_qq2D_ */
+ 
+ 
+ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+ ;;; Fixed-point -> double conversions.
+ 
+ #ifdef F7MOD_D2qq_
+ _DEFUN __fractdfqq
+     ;; Multiply with 2^{24+7} to get a QQ result in r25.
+     subi    r24, dex_lo (-31)
+     sbci    r25, dex_hi (-31)
+     XCALL   __fixdfsi
+     mov     r24, r25
+     ret
+ _ENDF __fractdfqq
+ #endif /* F7MOD_D2qq_ */
+ 
+ #ifdef F7MOD_D2uqq_
+ _DEFUN __fractdfuqq
+     ;; Multiply with 2^{24+8} to get a UQQ result in r25.
+     subi    r25, dex_hi (-32)
+     XCALL   __fixunsdfsi
+     mov     r24, r25
+     ret
+ _ENDF __fractdfuqq
+ #endif /* F7MOD_D2uqq_ */
+ 
+ #ifdef F7MOD_D2ha_
+ _DEFUN __fractdfha
+     ;; Multiply with 2^{16+7} to get a HA result in r25:r24
+     subi    r24, dex_lo (-23)
+     sbci    r25, dex_hi (-23)
+     XJMP    __fixdfsi
+ _ENDF __fractdfha
+ #endif /* F7MOD_D2ha_ */
+ 
+ #ifdef F7MOD_D2uha_
+ _DEFUN __fractdfuha
+     ;; Multiply with 2^24 to get a UHA result in r25:r24.
+     subi    r24, dex_lo (-24)
+     sbci    r25, dex_hi (-24)
+     XJMP    __fixunsdfsi
+ _ENDF __fractdfuha
+ #endif /* F7MOD_D2uha_ */
+ 
+ #ifdef F7MOD_D2hq_
+ _DEFUN __fractdfhq
+     ;; Multiply with 2^{16+15} to get a HQ result in r25:r24
+     ;; resp. with 2^31 to get a SQ result in r25:r22.
+ _LABEL __fractdfsq
+     subi    r24, dex_lo (-31)
+     sbci    r25, dex_hi (-31)
+     XJMP    __fixdfsi
+ _ENDF __fractdfhq
+ #endif /* F7MOD_D2hq_ */
+ 
+ #ifdef F7MOD_D2uhq_
+ _DEFUN __fractdfuhq
+     ;; Multiply with 2^{16+16} to get a UHQ result in r25:r24
+     ;; resp. with 2^32 to get a USQ result in r25:r22.
+ _LABEL  __fractdfusq
+     subi    r25, dex_hi (-32)
+     XJMP    __fixunsdfsi
+ _ENDF __fractdfuhq
+ #endif /* F7MOD_D2uhq_ */
+ 
+ #ifdef F7MOD_D2sa_
+ _DEFUN __fractdfsa
+     ;; Multiply with 2^15 to get a SA result in r25:r22.
+     subi    r24, dex_lo (-15)
+     sbci    r25, dex_hi (-15)
+     XJMP    __fixdfsi
+ _ENDF __fractdfsa
+ #endif /* F7MOD_D2sa_ */
+ 
+ #ifdef F7MOD_D2usa_
+ _DEFUN __fractdfusa
+     ;; Multiply with 2^16 to get a USA result in r25:r22.
+     subi    r25, dex_hi (-16)
+     XJMP    __fixunsdfsi
+ _ENDF __fractdfusa
+ #endif /* F7MOD_D2usa_ */
+ 
+ 
+ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+ ;;; [u]int32_t -> double conversions.
+ 
+ ;; double __floatsidf (int32_t);
+ #ifdef F7MOD_D_floatsidf_
+ _DEFUN __floatsidf
+     bst     r25, 7
+     brtc    0f
+     XCALL   __negsi2
+ 0:  XJMP    __floatunsidf.ge0
+ _ENDF __floatsidf
+ #endif /* F7MOD_D_floatsidf_ */
+ 
+ ;; double __floatunsidf (uint32_t);
+ #ifdef F7MOD_D_floatunsidf_
+ _DEFUN __floatunsidf
+     clt
+ _LABEL __floatunsidf.ge0
+     ;; Zero-extend SI at the low end.
+     clr     r18
+     clr     r19
+     wmov    r20,    r18
+     ;; Input is zero?
+     sbiw    r24,    0
+     sbci    r23,    0
+     sbci    r22,    0
+     breq 9f
+     ;; No: The double exponent of 0x80000000 is 31 plus a bias of 1023.
+     ;; Align the SI value such that the MSBit is as R25.4.
+     ;; For each << we have to subtract 1 from the exponent, and for
+     ;; each >> we have to add 1.  Since we want the MSB in R25.4 and
+     ;; not in R25.7, the initial exponent must be reduced by 3.
+     ldi     Xl,     dex_lo (31 + 1023 - 3)
+     ldi     Xh,     dex_hi (31 + 1023 - 3)
+     ;; Move the MSByte to R25.
+ 1:  tst     r25
+     brne 2f
+     subi    Xl,     dex_lo (8)
+     sbci    Xh,     dex_hi (8)
+     mov     r25,    r24
+     mov     r24,    r23
+     mov     r23,    r22
+     clr     r22
+     rjmp    1b
+ 2:  ;; Now we have R25 != 0.
+     cpi     r25,    0x20
+     brlo 3f
+     adiw    Xl,     DEX16 (1)
+     lsr     r25
+     ror     r24
+     ror     r23
+     ror     r22
+     ror     r21
+     rjmp 2b
+ 3:  cpi     r25,    0x10
+     brsh 4f
+     sbiw    Xl,     DEX16 (1)
+     lsl     r22
+     rol     r23
+     rol     r24
+     rol     r25
+     rjmp 3b
+ 4:  ;; Move the mantissa into place and clear the redundant leading 1.
+     cbr     r25,    0x10
+     mov     r20,    r21
+     mov     r21,    r22
+     mov     r22,    r23
+     mov     r23,    r24
+     mov     r24,    r25
+     ;; Insert the biased exponent.
+     or      r24,    Xl
+     mov     r25,    Xh
+     ;; Insert the sign.
+     bld     r25,    7
+ 9:  ret
+ _ENDF __floatunsidf
+ #endif /* F7MOD_D_floatunsidf_ */
+ 
+ 
  #endif /* !AVR_TINY */
diff -Nrcpad gcc-15-20251004/libgcc/config/avr/libf7/libf7-common.mk gcc-15-20251011/libgcc/config/avr/libf7/libf7-common.mk
*** gcc-15-20251004/libgcc/config/avr/libf7/libf7-common.mk	Sat Oct  4 22:34:05 2025
--- gcc-15-20251011/libgcc/config/avr/libf7/libf7-common.mk	Sat Oct 11 22:34:38 2025
*************** F7_ASM_PARTS += addsub_mant_scaled store
*** 22,40 ****
  F7_ASM_PARTS += to_integer to_unsigned clz normalize_with_carry normalize
  F7_ASM_PARTS += store_expo sqrt16 sqrt_approx div
  
! F7_ASM_PARTS += D_class D_fma D_powi
  F7_ASM_PARTS += D_isnan D_isinf D_isfinite D_signbit D_copysign D_neg D_fabs
  
  F7_ASM_PARTS += call_dd call_ddd
  
  # Stuff that will be wrapped in f7-wraps.h (included by libf7-asm.sx)
  # and give f7_asm_D_*.o modules.
  g_ddd += add sub mul div
! g_xdd_cmp += le lt ge gt ne eq unord
! g_dx += floatunsidf floatsidf extendsfdf2
  g_xd += fixdfsi fixdfdi fixunsdfdi fixunsdfsi truncdfsf2
  
! m_ddd += pow fmin fmax fmod hypot atan2 fdim
  m_ddx += ldexp frexp
  m_dd += sqrt cbrt exp exp10 pow10 log log10 log2 sin cos tan cotan asin acos atan
  m_dd += ceil floor trunc round sinh cosh tanh
--- 22,52 ----
  F7_ASM_PARTS += to_integer to_unsigned clz normalize_with_carry normalize
  F7_ASM_PARTS += store_expo sqrt16 sqrt_approx div
  
! F7_ASM_PARTS += D_class D_fma D_powi D_sincos
  F7_ASM_PARTS += D_isnan D_isinf D_isfinite D_signbit D_copysign D_neg D_fabs
+ F7_ASM_PARTS += D_cmp D_eq D_ne D_ge D_gt D_le D_lt D_unord D_fminfmax
  
  F7_ASM_PARTS += call_dd call_ddd
  
+ # Fixed-point -> double conversions
+ F7_ASM_PARTS += qq2D uqq2D            sq2D usq2D
+ F7_ASM_PARTS +=            ha2D uha2D sa2D usa2D
+ 
+ # Double -> fixed-point conversions
+ F7_ASM_PARTS += D2qq D2uqq D2hq D2uhq
+ F7_ASM_PARTS +=            D2ha D2uha D2sa D2usa
+ 
+ # Integer -> double conversions
+ F7_ASM_PARTS += D_floatsidf D_floatunsidf
+ 
  # Stuff that will be wrapped in f7-wraps.h (included by libf7-asm.sx)
  # and give f7_asm_D_*.o modules.
  g_ddd += add sub mul div
! g_xdd_cmp +=
! g_dx += extendsfdf2
  g_xd += fixdfsi fixdfdi fixunsdfdi fixunsdfsi truncdfsf2
  
! m_ddd += pow fmod hypot atan2 fdim
  m_ddx += ldexp frexp
  m_dd += sqrt cbrt exp exp10 pow10 log log10 log2 sin cos tan cotan asin acos atan
  m_dd += ceil floor trunc round sinh cosh tanh
*************** F7F += set_eps set_1pow2
*** 82,88 ****
  
  # Renames for ALIASes without own module.
  F7F += min max exp10
! F7F += floatunsidf floatsidf extendsfdf2
  F7F += fixdfsi fixdfdi fixunsdfdi fixunsdfsi truncdfsf2
  
  # Renames for f7-const.def.
--- 94,100 ----
  
  # Renames for ALIASes without own module.
  F7F += min max exp10
! F7F += extendsfdf2
  F7F += fixdfsi fixdfdi fixunsdfdi fixunsdfsi truncdfsf2
  
  # Renames for f7-const.def.
diff -Nrcpad gcc-15-20251004/libgcc/config/avr/libf7/libf7.c gcc-15-20251011/libgcc/config/avr/libf7/libf7.c
*** gcc-15-20251004/libgcc/config/avr/libf7/libf7.c	Sat Oct  4 22:34:05 2025
--- gcc-15-20251011/libgcc/config/avr/libf7/libf7.c	Sat Oct 11 22:34:38 2025
*************** f7_t* f7_set_s32 (f7_t *cc, int32_t i32)
*** 207,213 ****
    cc->flags = flags;
    return cc;
  }
- ALIAS (f7_set_s32, f7_floatsidf)
  #endif // F7MOD_set_s32_
  
  
--- 207,212 ----
*************** f7_t* f7_set_u32 (f7_t *cc, uint32_t u32
*** 219,225 ****
    cc->expo = 31;
    return f7_normalize_asm (cc);
  }
- ALIAS (f7_set_u32, f7_floatunsidf)
  #endif // F7MOD_set_u32_
  
  
--- 218,223 ----
