diff -Nrcpad gcc-15-20251101/LAST_UPDATED gcc-15-20251108/LAST_UPDATED
*** gcc-15-20251101/LAST_UPDATED	Sat Nov  1 22:35:54 2025
--- gcc-15-20251108/LAST_UPDATED	Sat Nov  8 22:33:41 2025
***************
*** 1 ****
! Obtained from git: releases/gcc-15 revision 31d3f96b790c76df14e6328fd600d616ca969abd
--- 1 ----
! Obtained from git: releases/gcc-15 revision 2935ce0a7836e1b7db85b1578b47fc5246dec7d0
diff -Nrcpad gcc-15-20251101/MD5SUMS gcc-15-20251108/MD5SUMS
*** gcc-15-20251101/MD5SUMS	Sat Nov  1 22:35:58 2025
--- gcc-15-20251108/MD5SUMS	Sat Nov  8 22:33:45 2025
***************
*** 1,5 ****
  # This file contains the MD5 checksums of the files in the
! # gcc-15-20251101.tar.xz tarball.
  #
  # Besides verifying that all files in the tarball were correctly expanded,
  # it also can be used to determine if any files have changed since the
--- 1,5 ----
  # This file contains the MD5 checksums of the files in the
! # gcc-15-20251108.tar.xz tarball.
  #
  # Besides verifying that all files in the tarball were correctly expanded,
  # it also can be used to determine if any files have changed since the
*************** d32239bcb673463ab874e80d47fae504  COPYIN
*** 25,31 ****
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--- 25,31 ----
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*** 563,569 ****
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--- 563,569 ----
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*** 776,782 ****
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--- 776,782 ----
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*************** f32c4d3d5df9ad9663b4978f7f8a2573  gcc/ad
*** 2990,2996 ****
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--- 2990,2996 ----
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*************** ce627f4de03a506a4263a68742891105  gcc/co
*** 3772,3787 ****
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--- 3772,3787 ----
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*************** cc4d538f7d66895b427db54b9660a953  gcc/co
*** 4939,4945 ****
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--- 4939,4945 ----
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*************** a9c3cddee4e237141062720b72fe38cd  gcc/co
*** 5499,5505 ****
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--- 5499,5505 ----
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*************** e5ccdda9d62d96ac397910d0fa391b0a  gcc/cp
*** 5561,5567 ****
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--- 5561,5567 ----
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*************** c2a7409e57253e5d9bfd8ce29fb85212  gcc/cp
*** 5579,5585 ****
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--- 5579,5585 ----
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*************** a798cdca802a57ffa3473ab610b37c86  gcc/fo
*** 6059,6065 ****
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--- 6059,6065 ----
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*************** ed475e0212369987bb572e7eabb4b4d7  gcc/lo
*** 6635,6641 ****
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--- 6635,6641 ----
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*************** b1497a03867668af210c32280876fdd7  gcc/sy
*** 8446,8452 ****
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--- 8446,8452 ----
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*************** c8f6159c50d59c6586f5797b42391c86  gcc/te
*** 26707,26712 ****
--- 26707,26714 ----
  1e129f71b6c51e2bb4325ececab6e9d0  gcc/testsuite/g++.dg/modules/inst-4_b.C
  9c1e5aa4fca91a8158a8ba8a5acab036  gcc/testsuite/g++.dg/modules/inst-5_a.H
  45ff01b5a1d0276885e30fb3445f5ed3  gcc/testsuite/g++.dg/modules/inst-5_b.C
+ 60bae6f4a7bfe8ecf40c92bc84aa9a4f  gcc/testsuite/g++.dg/modules/inst-6_a.C
+ 78bafa91ce71486fc147f8fef051956f  gcc/testsuite/g++.dg/modules/inst-6_b.C
  a345a5bfe397e84c45d084024a9acbf2  gcc/testsuite/g++.dg/modules/internal-1.C
  e6b16a33fb2c85abf4f99ad0d5ad33bb  gcc/testsuite/g++.dg/modules/internal-10.C
  8fe7459b1e2ebdf33715cdab3dbafaf9  gcc/testsuite/g++.dg/modules/internal-11.C
*************** c087af9321ac0e24731d2a4d1bb3e319  gcc/te
*** 26716,26721 ****
--- 26718,26724 ----
  4fffea4cdfd477df735c06f198229d8f  gcc/testsuite/g++.dg/modules/internal-14_a.C
  10a79d90c63564fa8794a477cbcaed50  gcc/testsuite/g++.dg/modules/internal-14_b.C
  f3dc43a1a76c9644a2c2a98b1094e62a  gcc/testsuite/g++.dg/modules/internal-14_c.C
+ 88ee381d96387e16394444459f265bfd  gcc/testsuite/g++.dg/modules/internal-16.C
  c66d17d0fb2dc80371978510d0cc1f0f  gcc/testsuite/g++.dg/modules/internal-2_a.H
  21bb55995bb6fa8ed6a8fa69368f7f36  gcc/testsuite/g++.dg/modules/internal-2_b.H
  ba3bc4f8f333742fb78f03db052c4ffa  gcc/testsuite/g++.dg/modules/internal-2_c.C
*************** ed132fcfade8212b992e822b341be9eb  gcc/te
*** 89580,89585 ****
--- 89583,89589 ----
  eda1f0d5c82c50988ede53858da3cabd  gcc/testsuite/gcc.target/riscv/rvv/autovec/pr121780.c
  cbc44c5c7fa77e3f0d3efc55779bba4b  gcc/testsuite/gcc.target/riscv/rvv/autovec/pr121781.c
  ca9ef4de6ed36716b972a6b4efc63e85  gcc/testsuite/gcc.target/riscv/rvv/autovec/pr121845.c
+ e990c042b373d09f16b69f4b30f0ac20  gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122321.c
  ee8bcba5f6876f2027f0f263f81465aa  gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-1.c
  7ff884bfa2e6cf9bc4c6172466538515  gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-10.c
  b2792e9264dcd6fa2e88f495d51677e6  gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-11.c
*************** c68a73138459484ead0cddce6ce27d08  gcc/te
*** 91753,91758 ****
--- 91757,91763 ----
  eaed30eccbeb952165411cfd2c789b72  gcc/testsuite/gcc.target/riscv/rvv/base/pr118872.c
  96272d16f134fa97f27114f27089793a  gcc/testsuite/gcc.target/riscv/rvv/base/pr118931-run-1.c
  b8ddadeddd15bd6f079e943b9036825d  gcc/testsuite/gcc.target/riscv/rvv/base/pr119115.c
+ 250f19182eb5aac9b6a01d7c594e8f5f  gcc/testsuite/gcc.target/riscv/rvv/base/pr122270-1.c
  c05efbdfaafc64ad34b3d1c4b60a38eb  gcc/testsuite/gcc.target/riscv/rvv/base/pr90263.c
  be75fd39ea9b3d01e3e22294359fb482  gcc/testsuite/gcc.target/riscv/rvv/base/pragma-2.c
  20a3b581af8087da2c1170d56ff52971  gcc/testsuite/gcc.target/riscv/rvv/base/pragma-3.c
diff -Nrcpad gcc-15-20251101/gcc/ChangeLog gcc-15-20251108/gcc/ChangeLog
*** gcc-15-20251101/gcc/ChangeLog	Sat Nov  1 22:32:35 2025
--- gcc-15-20251108/gcc/ChangeLog	Sat Nov  8 22:32:19 2025
***************
*** 1,3 ****
--- 1,64 ----
+ 2025-11-06  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	Backported from master:
+ 	2025-11-06  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	PR target/122516
+ 	* config/avr/elf.h (SUPPORTS_SHF_GNU_RETAIN): Define if
+ 	HAVE_GAS_SHF_GNU_RETAIN.
+ 
+ 2025-11-06  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	Backported from master:
+ 	2025-11-06  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	* config/avr/avr.cc (avr_output_addr_vec): Output
+ 	a valid opcode prior to the first gs() label provided:
+ 	- The code is compiled for an arch that has AVR-SD mcus, and
+ 	- the function has a "section" attribute, and
+ 	- the function has a gs() label addresses switch/case table.
+ 
+ 2025-11-03  Jeff Law  <jlaw@ventanamicro.com>
+ 
+ 	Backported from master:
+ 	2025-11-01  Jeff Law  <jlaw@ventanamicro.com>
+ 
+ 	PR rtl-optimization/122321
+ 	* lra-constraints.cc (update_equiv): Make sure REGNO is in
+ 	ira_reg_equiv before trying to update ira_reg_equiv.
+ 
+ 2025-11-03  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	Backported from master:
+ 	2025-10-26  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	PR target/122270
+ 	* config/riscv/riscv-vector-builtins-bases.cc (vset::fold): Use the
+ 	unshare_expr for the statement that will be added seperately rather
+ 	the one which will be used for the replacement.
+ 
+ 2025-11-02  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	Backported from master:
+ 	2025-11-02  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	PR target/122527
+ 	* config/avr/avr.cc (avr_load_libgcc_p): Return false if
+ 	the address-space is not ADDR_SPACE_FLASH.
+ 	(avr_out_lpm_no_lpmx [addr=REG]): Handle sizes of 3 and 4 bytes.
+ 
+ 2025-11-02  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	Backported from master:
+ 	2025-11-02  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	PR tree-optimization/118012
+ 	PR tree-optimization/122505
+ 	* config/avr/avr.md (mulpsi3): Also allow the insn condition
+ 	in the case where avropt_pr118012 && !AVR_TINY.
+ 	(*mulpsi3): Handle split for the !AVR_HAVE_MUL case.
+ 	(*mulpsi3-nomul.libgcc_split, *mulpsi3-nomul.libgcc): New insns.
+ 
  2025-10-31  Tamar Christina  <tamar.christina@arm.com>
  
  	Backported from master:
diff -Nrcpad gcc-15-20251101/gcc/DATESTAMP gcc-15-20251108/gcc/DATESTAMP
*** gcc-15-20251101/gcc/DATESTAMP	Sat Nov  1 22:32:36 2025
--- gcc-15-20251108/gcc/DATESTAMP	Sat Nov  8 22:32:21 2025
***************
*** 1 ****
! 20251101
--- 1 ----
! 20251108
diff -Nrcpad gcc-15-20251101/gcc/ada/ChangeLog gcc-15-20251108/gcc/ada/ChangeLog
*** gcc-15-20251101/gcc/ada/ChangeLog	Sat Nov  1 22:32:36 2025
--- gcc-15-20251108/gcc/ada/ChangeLog	Sat Nov  8 22:32:21 2025
***************
*** 1,3 ****
--- 1,14 ----
+ 2025-11-04  Bob Duff  <duff@adacore.com>
+ 
+ 	PR ada/118208
+ 	* exp_ch5.adb
+ 	(Expand_Assign_With_Target_Names.Replace_Target):
+ 	Remove code setting Entity to Empty.
+ 	* sinfo.ads (Has_Target_Names):
+ 	Improve comment: add "@" to clarify what "target name"
+ 	means, and remove the content-free phrase "and must
+ 	be expanded accordingly."
+ 
  2025-10-24  Eric Botcazou  <ebotcazou@adacore.com>
  
  	PR ada/118782
diff -Nrcpad gcc-15-20251101/gcc/ada/exp_ch5.adb gcc-15-20251108/gcc/ada/exp_ch5.adb
*** gcc-15-20251101/gcc/ada/exp_ch5.adb	Sat Nov  1 22:32:36 2025
--- gcc-15-20251108/gcc/ada/exp_ch5.adb	Sat Nov  8 22:32:22 2025
*************** package body Exp_Ch5 is
*** 2254,2260 ****
        function Replace_Target (N : Node_Id) return Traverse_Result;
        --  Replace occurrences of the target name by the proper entity: either
        --  the entity of the LHS in simple cases, or the formal of the
!       --  constructed procedure otherwise.
  
        --------------------
        -- Replace_Target --
--- 2254,2261 ----
        function Replace_Target (N : Node_Id) return Traverse_Result;
        --  Replace occurrences of the target name by the proper entity: either
        --  the entity of the LHS in simple cases, or the formal of the
!       --  constructed procedure otherwise. Mark all nodes as Analyzed=False
!       --  so reanalysis will occur.
  
        --------------------
        -- Replace_Target --
*************** package body Exp_Ch5 is
*** 2264,2283 ****
        begin
           if Nkind (N) = N_Target_Name then
              Rewrite (N, New_Occurrence_Of (Ent, Sloc (N)));
- 
-          --  The expression will be reanalyzed when the enclosing assignment
-          --  is reanalyzed, so reset the entity, which may be a temporary
-          --  created during analysis, e.g. a loop variable for an iterated
-          --  component association. However, if entity is callable then
-          --  resolution has established its proper identity (including in
-          --  rewritten prefixed calls) so we must preserve it.
- 
-          elsif Is_Entity_Name (N) then
-             if Present (Entity (N))
-               and then not Is_Overloadable (Entity (N))
-             then
-                Set_Entity (N, Empty);
-             end if;
           end if;
  
           Set_Analyzed (N, False);
--- 2265,2270 ----
diff -Nrcpad gcc-15-20251101/gcc/ada/sinfo.ads gcc-15-20251108/gcc/ada/sinfo.ads
*** gcc-15-20251101/gcc/ada/sinfo.ads	Sat Nov  1 22:32:37 2025
--- gcc-15-20251108/gcc/ada/sinfo.ads	Sat Nov  8 22:32:23 2025
*************** package Sinfo is
*** 1477,1483 ****
  
     --  Has_Target_Names
     --    Present in assignment statements. Indicates that the RHS contains
!    --    target names (see AI12-0125-3) and must be expanded accordingly.
  
     --  Has_Wide_Character
     --    Present in string literals, set if any wide character (i.e. character
--- 1477,1483 ----
  
     --  Has_Target_Names
     --    Present in assignment statements. Indicates that the RHS contains
!    --    target names ("@" -- see AI12-0125-3).
  
     --  Has_Wide_Character
     --    Present in string literals, set if any wide character (i.e. character
diff -Nrcpad gcc-15-20251101/gcc/config/avr/avr.cc gcc-15-20251108/gcc/config/avr/avr.cc
*** gcc-15-20251101/gcc/config/avr/avr.cc	Sat Nov  1 22:32:37 2025
--- gcc-15-20251108/gcc/config/avr/avr.cc	Sat Nov  8 22:32:25 2025
*************** avr_load_libgcc_p (rtx op)
*** 3293,3299 ****
  
    return (n_bytes > 2
  	  && !AVR_HAVE_LPMX
! 	  && avr_mem_flash_p (op));
  }
  
  
--- 3293,3300 ----
  
    return (n_bytes > 2
  	  && !AVR_HAVE_LPMX
! 	  && avr_mem_flash_p (op)
! 	  && MEM_ADDR_SPACE (op) == ADDR_SPACE_FLASH);
  }
  
  
*************** avr_out_lpm_no_lpmx (rtx_insn *insn, rtx
*** 3645,3650 ****
--- 3646,3691 ----
  	    avr_asm_len ("sbiw %2,1", xop, plen, 1);
  
  	  break; /* 2 */
+ 
+ 	/* cases 3 and 4 are only needed with ELPM but no ELPMx.  */
+ 
+ 	case 3:
+ 	  if (REGNO (dest) == REG_Z - 2
+ 	      && !reg_unused_after (insn, all_regs_rtx[REG_31]))
+ 	    avr_asm_len ("push r31", xop, plen, 1);
+ 
+ 	  avr_asm_len ("%4lpm $ mov %A0,%3 $ adiw %2,1", xop, plen, 3);
+ 	  avr_asm_len ("%4lpm $ mov %B0,%3 $ adiw %2,1", xop, plen, 3);
+ 	  avr_asm_len ("%4lpm $ mov %C0,%3", xop, plen, 2);
+ 
+ 	  if (REGNO (dest) == REG_Z - 2)
+ 	    {
+ 	      if (!reg_unused_after (insn, all_regs_rtx[REG_31]))
+ 		avr_asm_len ("pop r31", xop, plen, 1);
+ 	    }
+ 	  else if (!reg_unused_after (insn, addr))
+ 	    avr_asm_len ("sbiw %2,2", xop, plen, 1);
+ 
+ 	  break; /* 3 */
+ 
+ 	case 4:
+ 	  avr_asm_len ("%4lpm $ mov %A0,%3 $ adiw %2,1", xop, plen, 3);
+ 	  avr_asm_len ("%4lpm $ mov %B0,%3 $ adiw %2,1", xop, plen, 3);
+ 	  if (REGNO (dest) != REG_Z - 2)
+ 	    {
+ 	      avr_asm_len ("%4lpm $ mov %C0,%3 $ adiw %2,1", xop, plen, 3);
+ 	      avr_asm_len ("%4lpm $ mov %D0,%3", xop, plen, 2);
+ 	      if (!reg_unused_after (insn, addr))
+ 		avr_asm_len ("sbiw %2,3", xop, plen, 1);
+ 	    }
+ 	  else
+ 	    {
+ 	      avr_asm_len ("%4lpm $ push %3 $ adiw %2,1", xop, plen, 3);
+ 	      avr_asm_len ("%4lpm $ mov %D0,%3", xop, plen, 2);
+ 	      avr_asm_len ("pop $C0", xop, plen, 1);
+ 	    }
+ 
+ 	  break; /* 4 */
  	}
  
        break; /* REG */
*************** avr_output_addr_vec (rtx_insn *labl, rtx
*** 14406,14411 ****
--- 14447,14462 ----
  {
    FILE *stream = asm_out_file;
  
+   // AVR-SD: On functional safety devices, each executed instruction must
+   // be followed by a valid opcode.  This is because instruction validation
+   // runs at fetch and decode for the next instruction and while the 2-stage
+   // pipeline is executing the current one.  There is no multilib option for
+   // these devices, so take all multilib variants that contain AVR-SD.
+   const bool maybe_sd = (AVR_HAVE_JMP_CALL
+ 			 && (avr_arch_index == ARCH_AVRXMEGA2
+ 			     || avr_arch_index == ARCH_AVRXMEGA3));
+   bool uses_subsection = false;
+ 
    app_disable ();
  
    // Switch to appropriate (sub)section.
*************** avr_output_addr_vec (rtx_insn *labl, rtx
*** 14419,14424 ****
--- 14470,14476 ----
  
        switch_to_section (current_function_section ());
        fprintf (stream, "\t.subsection\t1\n");
+       uses_subsection = true;
      }
    else
      {
*************** avr_output_addr_vec (rtx_insn *labl, rtx
*** 14441,14450 ****
  	       AVR_HAVE_JMP_CALL ? "a" : "ax");
      }
  
-   // Output the label that precedes the table.
- 
    ASM_OUTPUT_ALIGN (stream, 1);
  
    char s_labl[40];
    targetm.asm_out.generate_internal_label (s_labl, "L",
  					   CODE_LABEL_NUMBER (labl));
--- 14493,14513 ----
  	       AVR_HAVE_JMP_CALL ? "a" : "ax");
      }
  
    ASM_OUTPUT_ALIGN (stream, 1);
  
+   if (maybe_sd && uses_subsection)
+     {
+       // Insert a valid opcode prior to the first gs() label.
+       // Any valid opcode will do.  Use CLH since it disassembles
+       // more nicely than NOP = 0x0000.  This is all GCC can do.
+       // Other cases, like inserting CLH after the vector table and
+       // after the last instruction, are handled by other parts of
+       // the toolchain.
+       fprintf (stream, "\tclh\n");
+     }
+ 
+   // Output the label that precedes the table.
+ 
    char s_labl[40];
    targetm.asm_out.generate_internal_label (s_labl, "L",
  					   CODE_LABEL_NUMBER (labl));
diff -Nrcpad gcc-15-20251101/gcc/config/avr/avr.md gcc-15-20251108/gcc/config/avr/avr.md
*** gcc-15-20251101/gcc/config/avr/avr.md	Sat Nov  1 22:32:37 2025
--- gcc-15-20251108/gcc/config/avr/avr.md	Sat Nov  8 22:32:25 2025
***************
*** 4091,4099 ****
                               (match_operand:PSI 2 "nonmemory_operand" "")))
                (clobber (reg:HI 26))
                (clobber (reg:DI 18))])]
!   "AVR_HAVE_MUL"
    {
!     if (s8_operand (operands[2], PSImode))
        {
          rtx reg = force_reg (QImode, gen_int_mode (INTVAL (operands[2]), QImode));
          emit_insn (gen_mulsqipsi3 (operands[0], reg, operands[1]));
--- 4091,4107 ----
                               (match_operand:PSI 2 "nonmemory_operand" "")))
                (clobber (reg:HI 26))
                (clobber (reg:DI 18))])]
!   "AVR_HAVE_MUL
!    || (avropt_pr118012
!        /* AVR_TINY passes args on the stack, so we cannot work
!           around PR118012 like this. */
!        && ! AVR_TINY)"
    {
!     if (!AVR_HAVE_MUL)
!       {
!         operands[2] = force_reg (PSImode, operands[2]);
!       }
!     else if (s8_operand (operands[2], PSImode))
        {
          rtx reg = force_reg (QImode, gen_int_mode (INTVAL (operands[2]), QImode));
          emit_insn (gen_mulsqipsi3 (operands[0], reg, operands[1]));
***************
*** 4198,4204 ****
                    (match_operand:PSI 2 "pseudo_register_or_const_int_operand" "rn")))
     (clobber (reg:HI 26))
     (clobber (reg:DI 18))]
!   "AVR_HAVE_MUL && !reload_completed"
    { gcc_unreachable(); }
    "&& 1"
    [(set (reg:PSI 18)
--- 4206,4214 ----
                    (match_operand:PSI 2 "pseudo_register_or_const_int_operand" "rn")))
     (clobber (reg:HI 26))
     (clobber (reg:DI 18))]
!   "!reload_completed
!    && (AVR_HAVE_MUL
!        || (avropt_pr118012 && !AVR_TINY))"
    { gcc_unreachable(); }
    "&& 1"
    [(set (reg:PSI 18)
***************
*** 4208,4220 ****
     (parallel [(set (reg:PSI 22)
                     (mult:PSI (reg:PSI 22)
                               (reg:PSI 18)))
!               (clobber (reg:QI 21))
!               (clobber (reg:QI 25))
!               (clobber (reg:HI 26))])
     (set (match_dup 0)
          (reg:PSI 22))]
    {
!     if (s8_operand (operands[2], PSImode))
        {
          rtx reg = force_reg (QImode, gen_int_mode (INTVAL (operands[2]), QImode));
          emit_insn (gen_mulsqipsi3 (operands[0], reg, operands[1]));
--- 4218,4247 ----
     (parallel [(set (reg:PSI 22)
                     (mult:PSI (reg:PSI 22)
                               (reg:PSI 18)))
!               (clobber (match_dup 3))
!               (clobber (match_dup 4))
!               (clobber (match_dup 5))])
     (set (match_dup 0)
          (reg:PSI 22))]
    {
!     if (AVR_HAVE_MUL)
!       {
!         operands[3] = gen_rtx_REG (QImode, REG_21);
!         operands[4] = gen_rtx_REG (QImode, REG_25);
!         operands[5] = gen_rtx_REG (HImode, REG_26);
!       }
!     else
!       {
!         operands[3] = gen_rtx_REG (SImode, REG_18);
!         operands[4] = gen_rtx_SCRATCH (QImode);
!         operands[5] = gen_rtx_SCRATCH (HImode);
!       }
! 
!     if (!AVR_HAVE_MUL)
!       {
!         operands[2] = force_reg (PSImode, operands[2]);
!       }
!     else if (s8_operand (operands[2], PSImode))
        {
          rtx reg = force_reg (QImode, gen_int_mode (INTVAL (operands[2]), QImode));
          emit_insn (gen_mulsqipsi3 (operands[0], reg, operands[1]));
***************
*** 4273,4278 ****
--- 4300,4336 ----
    "%~call __mulpsi3"
    [(set_attr "type" "xcall")])
  
+ (define_insn_and_split "*mulpsi3-nomul.libgcc_split"
+   [(set (reg:PSI 22)
+         (mult:PSI (reg:PSI 22)
+                   (reg:PSI 18)))
+    (clobber (reg:SI 18))
+    (clobber (scratch:QI))
+    (clobber (scratch:HI))]
+   "!AVR_HAVE_MUL && avropt_pr118012 && !AVR_TINY"
+   "#"
+   "&& reload_completed"
+   [(parallel [(set (reg:PSI 22)
+                    (mult:PSI (reg:PSI 22)
+                              (reg:PSI 18)))
+               (clobber (reg:SI 18))
+               (clobber (scratch:QI))
+               (clobber (scratch:HI))
+               (clobber (reg:CC REG_CC))])])
+ 
+ (define_insn "*mulpsi3-nomul.libgcc"
+   [(set (reg:PSI 22)
+         (mult:PSI (reg:PSI 22)
+                   (reg:PSI 18)))
+    (clobber (reg:SI 18))
+    (clobber (scratch:QI))
+    (clobber (scratch:HI))
+    (clobber (reg:CC REG_CC))]
+   "reload_completed
+    && !AVR_HAVE_MUL && avropt_pr118012 && !AVR_TINY"
+   "%~call __mulpsi3"
+   [(set_attr "type" "xcall")])
+ 
  
  ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  ;; 24-bit signed/unsigned division and modulo.
diff -Nrcpad gcc-15-20251101/gcc/config/avr/elf.h gcc-15-20251108/gcc/config/avr/elf.h
*** gcc-15-20251101/gcc/config/avr/elf.h	Sat Nov  1 22:32:37 2025
--- gcc-15-20251108/gcc/config/avr/elf.h	Sat Nov  8 22:32:25 2025
***************
*** 18,23 ****
--- 18,36 ----
     along with GCC; see the file COPYING3.  If not see
     <http://www.gnu.org/licenses/>.  */
  
+ /* defaults.h requires HAVE_INITFINI_ARRAY_SUPPORT to be present
+    in order for attribute "retain" to be recognized.  This is due
+    to some quirks in crtstuff.h -- which isn't even used by avr.
+    All we need is that Binutils supports the "R"etain section flag.
+    If that's the case, define SUPPORTS_SHF_GNU_RETAIN so that
+    defaults.h doesn't define it to 0.  */
+ #if defined(IN_GCC) && !defined(USED_FOR_TARGET) && !defined(GENERATOR_FILE)
+ #include "auto-host.h" /* HAVE_GAS_SHF_GNU_RETAIN */
+ #if HAVE_GAS_SHF_GNU_RETAIN
+ #undef SUPPORTS_SHF_GNU_RETAIN
+ #define SUPPORTS_SHF_GNU_RETAIN 1
+ #endif
+ #endif
  
  /* Overriding some definitions from elfos.h for AVR.  */
  
diff -Nrcpad gcc-15-20251101/gcc/config/riscv/riscv-vector-builtins-bases.cc gcc-15-20251108/gcc/config/riscv/riscv-vector-builtins-bases.cc
*** gcc-15-20251101/gcc/config/riscv/riscv-vector-builtins-bases.cc	Sat Nov  1 22:32:37 2025
--- gcc-15-20251108/gcc/config/riscv/riscv-vector-builtins-bases.cc	Sat Nov  8 22:32:25 2025
*************** public:
*** 1792,1803 ****
         The fold routines expect the replacement statement to have the
         same lhs as the original call, so return the copy statement
         rather than the field update.  */
!     gassign *copy = gimple_build_assign (unshare_expr (f.lhs), rhs_tuple);
  
      /* Get a reference to the individual vector.  */
      tree field = tuple_type_field (TREE_TYPE (f.lhs));
      tree lhs_array
!       = build3 (COMPONENT_REF, TREE_TYPE (field), f.lhs, field, NULL_TREE);
      tree lhs_vector = build4 (ARRAY_REF, TREE_TYPE (rhs_vector), lhs_array,
  			      index, NULL_TREE, NULL_TREE);
      gassign *update = gimple_build_assign (lhs_vector, rhs_vector);
--- 1792,1804 ----
         The fold routines expect the replacement statement to have the
         same lhs as the original call, so return the copy statement
         rather than the field update.  */
!     gassign *copy = gimple_build_assign (f.lhs, rhs_tuple);
  
      /* Get a reference to the individual vector.  */
      tree field = tuple_type_field (TREE_TYPE (f.lhs));
      tree lhs_array
!       = build3 (COMPONENT_REF, TREE_TYPE (field), unshare_expr (f.lhs),
! 		field, NULL_TREE);
      tree lhs_vector = build4 (ARRAY_REF, TREE_TYPE (rhs_vector), lhs_array,
  			      index, NULL_TREE, NULL_TREE);
      gassign *update = gimple_build_assign (lhs_vector, rhs_vector);
diff -Nrcpad gcc-15-20251101/gcc/cp/ChangeLog gcc-15-20251108/gcc/cp/ChangeLog
*** gcc-15-20251101/gcc/cp/ChangeLog	Sat Nov  1 22:32:38 2025
--- gcc-15-20251108/gcc/cp/ChangeLog	Sat Nov  8 22:32:25 2025
***************
*** 1,3 ****
--- 1,32 ----
+ 2025-11-04  Nathaniel Shead  <nathanieloshead@gmail.com>
+ 
+ 	Backported from master:
+ 	2025-11-04  Nathaniel Shead  <nathanieloshead@gmail.com>
+ 
+ 	PR c++/122253
+ 	* decl2.cc (min_vis_expr_r): Don't mark no-linkage declarations
+ 	as VISIBILITY_ANON.
+ 
+ 2025-11-02  Nathaniel Shead  <nathanieloshead@gmail.com>
+ 
+ 	Backported from master:
+ 	2025-11-02  Nathaniel Shead  <nathanieloshead@gmail.com>
+ 
+ 	PR c++/122421
+ 	* module.cc (trees_in::read_var_def): Don't handle class-scope
+ 	variables anymore.
+ 	(trees_in::read_class_def): Handle them here instead.
+ 
+ 2025-11-01  Nathaniel Shead  <nathanieloshead@gmail.com>
+ 
+ 	Backported from master:
+ 	2025-11-01  Nathaniel Shead  <nathanieloshead@gmail.com>
+ 
+ 	PR c++/122381
+ 	* module.cc (trees_out::core_vals): Write BASELINK_OPTYPE (aka
+ 	TREE_CHAIN).
+ 	(trees_in::core_vals): Read it.
+ 
  2025-10-28  Patrick Palka  <ppalka@redhat.com>
  
  	Backported from master:
diff -Nrcpad gcc-15-20251101/gcc/cp/decl2.cc gcc-15-20251108/gcc/cp/decl2.cc
*** gcc-15-20251101/gcc/cp/decl2.cc	Sat Nov  1 22:32:38 2025
--- gcc-15-20251108/gcc/cp/decl2.cc	Sat Nov  8 22:32:25 2025
*************** min_vis_expr_r (tree *tp, int */*walk_su
*** 2862,2868 ****
  	  break;
  	}
      addressable:
!       if (! TREE_PUBLIC (t))
  	tpvis = VISIBILITY_ANON;
        else
  	tpvis = DECL_VISIBILITY (t);
--- 2862,2873 ----
  	  break;
  	}
      addressable:
!       if (decl_linkage (t) == lk_none)
! 	tpvis = type_visibility (TREE_TYPE (t));
!       /* Decls that have had their visibility constrained will report
! 	 as external linkage, but we still want to transitively constrain
! 	 if we refer to them, so just check TREE_PUBLIC instead.  */
!       else if (!TREE_PUBLIC (t))
  	tpvis = VISIBILITY_ANON;
        else
  	tpvis = DECL_VISIBILITY (t);
diff -Nrcpad gcc-15-20251101/gcc/cp/module.cc gcc-15-20251108/gcc/cp/module.cc
*** gcc-15-20251101/gcc/cp/module.cc	Sat Nov  1 22:32:38 2025
--- gcc-15-20251108/gcc/cp/module.cc	Sat Nov  8 22:32:25 2025
*************** trees_in::read_var_def (tree decl, tree
*** 12848,12859 ****
  	  if (DECL_EXPLICIT_INSTANTIATION (decl)
  	      && !DECL_EXTERNAL (decl))
  	    setup_explicit_instantiation_definition_linkage (decl);
! 	  if (DECL_IMPLICIT_INSTANTIATION (decl)
! 	      || (DECL_EXPLICIT_INSTANTIATION (decl)
! 		  && !DECL_EXTERNAL (decl))
! 	      || (DECL_CLASS_SCOPE_P (decl)
! 		  && !DECL_VTABLE_OR_VTT_P (decl)
! 		  && !DECL_TEMPLATE_INFO (decl)))
  	    note_vague_linkage_variable (decl);
  	}
        if (!dyn_init)
--- 12848,12858 ----
  	  if (DECL_EXPLICIT_INSTANTIATION (decl)
  	      && !DECL_EXTERNAL (decl))
  	    setup_explicit_instantiation_definition_linkage (decl);
! 	  /* Class static data members are handled in read_class_def.  */
! 	  if (!DECL_CLASS_SCOPE_P (decl)
! 	      && (DECL_IMPLICIT_INSTANTIATION (decl)
! 		  || (DECL_EXPLICIT_INSTANTIATION (decl)
! 		      && !DECL_EXTERNAL (decl))))
  	    note_vague_linkage_variable (decl);
  	}
        if (!dyn_init)
*************** trees_in::read_class_def (tree defn, tre
*** 13267,13272 ****
--- 13266,13275 ----
  			DECL_ACCESS (d) = tree_cons (type, access, list);
  		    }
  		}
+ 
+ 	      if (TREE_CODE (decl) == VAR_DECL
+ 		  && TREE_CODE (maybe_template) != TEMPLATE_DECL)
+ 		note_vague_linkage_variable (decl);
  	    }
  	}
  
diff -Nrcpad gcc-15-20251101/gcc/fortran/ChangeLog gcc-15-20251108/gcc/fortran/ChangeLog
*** gcc-15-20251101/gcc/fortran/ChangeLog	Sat Nov  1 22:32:38 2025
--- gcc-15-20251108/gcc/fortran/ChangeLog	Sat Nov  8 22:32:25 2025
***************
*** 1,3 ****
--- 1,26 ----
+ 2025-11-01  Harald Anlauf  <anlauf@gmx.de>
+ 
+ 	Backported from master:
+ 	2025-10-25  Harald Anlauf  <anlauf@gmx.de>
+ 
+ 	PR fortran/114023
+ 	* trans-expr.cc (gfc_trans_pointer_assignment): Always set dtype
+ 	when remapping a pointer.  For unlimited polymorphic LHS use
+ 	elem_len from RHS.
+ 	* trans-intrinsic.cc (gfc_conv_is_contiguous_expr): Extend inline
+ 	generated code for IS_CONTIGUOUS for pointer arguments to detect
+ 	when span differs from the element size.
+ 
+ 2025-11-01  Harald Anlauf  <anlauf@gmx.de>
+ 
+ 	Backported from master:
+ 	2025-10-24  Harald Anlauf  <anlauf@gmx.de>
+ 
+ 	PR fortran/122386
+ 	* dependency.cc (gfc_ref_needs_temporary_p): Revert r16-518.
+ 	* trans-intrinsic.cc (gfc_conv_intrinsic_transfer): Force temporary
+ 	for SOURCE not being a simply-contiguous array.
+ 
  2025-10-25  Harald Anlauf  <anlauf@gmx.de>
  
  	Backported from master:
diff -Nrcpad gcc-15-20251101/gcc/lra-constraints.cc gcc-15-20251108/gcc/lra-constraints.cc
*** gcc-15-20251101/gcc/lra-constraints.cc	Sat Nov  1 22:32:39 2025
--- gcc-15-20251108/gcc/lra-constraints.cc	Sat Nov  8 22:32:26 2025
*************** update_equiv (int regno)
*** 522,527 ****
--- 522,532 ----
  {
    rtx x;
  
+   /* If REGNO is beyond the length of the equivalence array structure,
+      then there's nothing to update.  */
+   if (regno >= ira_reg_equiv_len)
+     return;
+ 
    if ((x = ira_reg_equiv[regno].memory) != NULL_RTX)
      ira_reg_equiv[regno].memory
        = simplify_replace_fn_rtx (x, NULL_RTX, loc_equivalence_callback,
diff -Nrcpad gcc-15-20251101/gcc/testsuite/ChangeLog gcc-15-20251108/gcc/testsuite/ChangeLog
*** gcc-15-20251101/gcc/testsuite/ChangeLog	Sat Nov  1 22:32:40 2025
--- gcc-15-20251108/gcc/testsuite/ChangeLog	Sat Nov  8 22:32:27 2025
***************
*** 1,3 ****
--- 1,61 ----
+ 2025-11-04  Nathaniel Shead  <nathanieloshead@gmail.com>
+ 
+ 	Backported from master:
+ 	2025-11-04  Nathaniel Shead  <nathanieloshead@gmail.com>
+ 
+ 	PR c++/122253
+ 	* g++.dg/modules/internal-16.C: New test.
+ 
+ 2025-11-03  Jeff Law  <jlaw@ventanamicro.com>
+ 
+ 	Backported from master:
+ 	2025-11-01  Jeff Law  <jlaw@ventanamicro.com>
+ 
+ 	PR rtl-optimization/122321
+ 	* gcc.target/riscv/rvv/autovec/pr122321.c: New test.
+ 
+ 2025-11-03  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	Backported from master:
+ 	2025-10-26  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	PR target/122270
+ 	* gcc.target/riscv/rvv/base/pr122270-1.c: New test.
+ 
+ 2025-11-02  Nathaniel Shead  <nathanieloshead@gmail.com>
+ 
+ 	Backported from master:
+ 	2025-11-02  Nathaniel Shead  <nathanieloshead@gmail.com>
+ 
+ 	PR c++/122421
+ 	* g++.dg/modules/inst-6_a.C: New test.
+ 	* g++.dg/modules/inst-6_b.C: New test.
+ 
+ 2025-11-01  Harald Anlauf  <anlauf@gmx.de>
+ 
+ 	Backported from master:
+ 	2025-10-25  Harald Anlauf  <anlauf@gmx.de>
+ 
+ 	PR fortran/114023
+ 	* gfortran.dg/is_contiguous_5.f90: New test.
+ 
+ 2025-11-01  Harald Anlauf  <anlauf@gmx.de>
+ 
+ 	Backported from master:
+ 	2025-10-24  Harald Anlauf  <anlauf@gmx.de>
+ 
+ 	PR fortran/122386
+ 	* gfortran.dg/transfer_array_subref_2.f90: New test.
+ 
+ 2025-11-01  Nathaniel Shead  <nathanieloshead@gmail.com>
+ 
+ 	Backported from master:
+ 	2025-11-01  Nathaniel Shead  <nathanieloshead@gmail.com>
+ 
+ 	PR c++/122381
+ 	* g++.dg/modules/convop-2_a.H: New test.
+ 	* g++.dg/modules/convop-2_b.C: New test.
+ 
  2025-10-31  Tamar Christina  <tamar.christina@arm.com>
  
  	Backported from master:
diff -Nrcpad gcc-15-20251101/gcc/testsuite/g++.dg/modules/inst-6_a.C gcc-15-20251108/gcc/testsuite/g++.dg/modules/inst-6_a.C
*** gcc-15-20251101/gcc/testsuite/g++.dg/modules/inst-6_a.C	Thu Jan  1 00:00:00 1970
--- gcc-15-20251108/gcc/testsuite/g++.dg/modules/inst-6_a.C	Sat Nov  8 22:32:33 2025
***************
*** 0 ****
--- 1,14 ----
+ // PR c++/122421
+ // { dg-additional-options "-fmodules" }
+ // { dg-module-cmi M }
+ 
+ export module M;
+ 
+ export template <typename T> struct Type {
+   static const int arr[3];
+ };
+ 
+ extern template const int Type<double>::arr[3];
+ template <typename T> const int Type<T>::arr[] = { 42, 43, 44 };
+ 
+ export Type<int> ti;
diff -Nrcpad gcc-15-20251101/gcc/testsuite/g++.dg/modules/inst-6_b.C gcc-15-20251108/gcc/testsuite/g++.dg/modules/inst-6_b.C
*** gcc-15-20251101/gcc/testsuite/g++.dg/modules/inst-6_b.C	Thu Jan  1 00:00:00 1970
--- gcc-15-20251108/gcc/testsuite/g++.dg/modules/inst-6_b.C	Sat Nov  8 22:32:33 2025
***************
*** 0 ****
--- 1,12 ----
+ // PR c++/122421
+ // { dg-additional-options "-fmodules" }
+ 
+ import M;
+ 
+ int main() {
+   const int& a = Type<int>::arr[0];
+   const int& b = Type<double>::arr[0];
+ }
+ 
+ // { dg-final { scan-assembler {_ZNW1M4TypeIiE3arrE:} } }
+ // { dg-final { scan-assembler-not {_ZNW1M4TypeIdE3arrE:} } }
diff -Nrcpad gcc-15-20251101/gcc/testsuite/g++.dg/modules/internal-16.C gcc-15-20251108/gcc/testsuite/g++.dg/modules/internal-16.C
*** gcc-15-20251101/gcc/testsuite/g++.dg/modules/internal-16.C	Thu Jan  1 00:00:00 1970
--- gcc-15-20251108/gcc/testsuite/g++.dg/modules/internal-16.C	Sat Nov  8 22:32:33 2025
***************
*** 0 ****
--- 1,30 ----
+ // PR c++/122253
+ // { dg-additional-options "-fmodules -Wtemplate-names-tu-local" }
+ 
+ export module M;
+ 
+ template <int> struct ic {};
+ struct S {
+   constexpr operator int() const { return 5; }
+   constexpr int operator&() const { return 8; }
+ };
+ 
+ template <typename T> inline void a(T) {
+   T a;
+   static T b;
+   ic<a>{};
+   ic<b>{};
+   ic<&a>{};
+   ic<&b>{};
+ }
+ 
+ template <typename T> inline auto b(T x) {
+   return [&](auto y) {
+     return [=](auto z) {
+       return ic<(int)x + (int)&y + (int)z>{};
+     };
+   };
+ }
+ 
+ template void a(S);
+ ic<5 + 8 + 5> x = b(S{})(S{})(S{});
diff -Nrcpad gcc-15-20251101/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122321.c gcc-15-20251108/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122321.c
*** gcc-15-20251101/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122321.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20251108/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122321.c	Sat Nov  8 22:32:59 2025
***************
*** 0 ****
--- 1,150 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv -mabi=lp64d -w -O0" { target rv64 } } */
+ /* { dg-options "-march=rv32gcv -mabi=ilp32 -w -O0" { target rv32 } } */
+ 
+ 
+ typedef int a;
+ typedef signed char b;
+ typedef char c;
+ typedef short d;
+ typedef unsigned short e;
+ typedef a f;
+ typedef unsigned g;
+ typedef long h;
+ h j, k, l, m, n, o;
+ int p, q, r, s;
+ short t;
+ volatile a u;
+ a v[];
+ char w, x;
+ a *y, *z;
+ a **aa;
+ __attribute__((always_inline)) b __attribute__((vector_size(16)))
+ ab(f __attribute__((vector_size(8 * sizeof(f)))), d ac,
+    d __attribute__((vector_size(2 * sizeof(d)))), d) {
+   return __builtin_shufflevector(
+       (b __attribute__((vector_size(16)))) __builtin_convertvector(
+           (d __attribute__((vector_size(16 *sizeof(d))))){
+               ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac},
+           c __attribute__((vector_size(16)))) |
+           __builtin_convertvector(
+               (d __attribute__((vector_size(16 *sizeof(d))))){
+                   ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac},
+               c __attribute__((vector_size(16)))),
+       __builtin_convertvector(
+           (d __attribute__((vector_size(16 *sizeof(d))))){
+               ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac, ac},
+           b __attribute__((vector_size(16)))),
+       3, 21, 0, 2, 2, 7, 1, 8, 4, 0, 8, 0, 8, 9, 5, 6);
+ }
+ __attribute__((always_inline)) g
+ ad(d ae, h __attribute__((vector_size(32 * sizeof(h))))) {
+   g f = 6318;
+   return (8 ? ae / 786856318u : 0) & ae;
+ }
+ a(af)(a, int);
+ void(ag)(long);
+ char(ah)(char, char);
+ char(ai)(char);
+ short(aj)(short, short);
+ int ak(long, int *, int *, char, int);
+ void al(signed, a *, int *, long);
+ char am(int *, short, short);
+ void an(int *, long, int);
+ void ao(int, int *, a *);
+ a ap() {
+   int *aq, *ar, *as;
+   short at;
+   char au, av, aw = 2;
+   long ax, ay, az = j;
+   int ba, i;
+   g __attribute__((vector_size(16 * sizeof(g)))) bb = {80};
+   b __attribute__((vector_size(4))) bc = {6};
+   int bd[1];
+   char *be = &w;
+   int bf, bg = q;
+   a **bh[] = {
+       &y, &z, &z, &y, &y, &y, &y, &y, &z, &z, &y, &z, &y, &y, &y, &y, &z, &y,
+       &z, &y, &y, &y, &z, &z, &z, &y, &z, &z, &z, &y, &z, &z, &y, &z, &z, &y,
+       &z, &z, &z, &y, 0,  &z, 0,  &y, 0,  &y, &y, &z, &z, &y, &y, 0,  &z, 0,
+       &z, 0,  &y, &z, &z, 0,  &z, 0,  &z, &z, &z, &y, &z, &z, &y, &z, &z, &y,
+       0,  &z, 0,  &z, &z, &y, 0,  &z, 0,  &y, 0,  &y, &y, &z, &z, &y, &y, 0,
+       &z, 0,  &z, 0,  &y, &z, &z, 0,  &z, 0,  &z, &z, &z, &y, &z, &z, &y, &z,
+       &z, &y, 0,  &z, 0,  &z, &z, &y, 0,  &z, 0,  &y, 0,  &y, &y, &z, &z, &y,
+       &y, 0,  &z, 0,  &z, 0,  &y, &z, &z, 0,  &z, 0,  &z, &z, &z, &y, &z, &z,
+       &y, &z, &z, &y, 0,  &z, 0,  &z, &z, &y, 0,  &z, 0,  &y, 0,  &y, &y, &z,
+       &z, &y, &y, 0,  &z, 0,  &z, 0,  &y, &z, &z, 0,  0,  &z, 0,  &z, &z, &z,
+       &y, &z, &z, &y, &z, &z, &y, 0,  &z, 0,  0,  &z, &z};
+   for (; i; i++)
+     bd[i] = p;
+   h __attribute__((vector_size(32 * sizeof(h))))
+   bi = {2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681,
+         2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681,
+         2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681, 2681},
+   bj = __builtin_convertvector(
+       (c __attribute__((vector_size(32)))){
+           aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw,
+           aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw, aw},
+       h __attribute__((vector_size(32 * sizeof(h))))),
+   bk = __builtin_convertvector(
+       __builtin_shufflevector(bb, bb, 4, 8, 7, 9, 1, 10, 4, 7, 0, 4, 3, 5, 6, 7,
+                               6, 2, 2, 20, 6, 4, 7, 7, 9, 7, 4, 9, 8, 6, 1, 0,
+                               6, 9),
+       h __attribute__((vector_size(32 * sizeof(h)))));
+   bb = __builtin_convertvector(
+       ab(__builtin_shufflevector(
+              __builtin_shufflevector(
+                  __builtin_convertvector(
+                      __builtin_shufflevector(bb, bb, 1, 31, 8, 2, 3, 7, 4, 0, 7,
+                                              3, 4, 6, 7, 1, 9, 3, 8, 7, 1, 8, 5,
+                                              3, 9, 9, 0, 3, 2, 8, 5, 2, 5, 3),
+                      f __attribute__((vector_size(32 * sizeof(f))))),
+                  (f __attribute__((vector_size(32 * sizeof(f))))){
+                      800761418310502961587690471176286910032020044212442466872080013589354162852207417903424527024812447907811618435019152886919380169872910001752451018659493155196043018716516518746289614523948734758456011127254301274351182132760058399143431214610613191313926994549901191890929084305862034120561651877003645},
+                  32, 44),
+              (f __attribute__((vector_size(2 * sizeof(f))))){o}, 1, 0, 3, 0, 2,
+              1, 3, 3),
+          ad(__builtin_clzg((g)aw, (f)bb[9]),
+             (h __attribute__((vector_size(32 * sizeof(h))))){
+                 bi[0] ?: bk[0],    bi[1] ? 1 : bk[1],  bi[2] ? 2 : bk[2],
+                 bi[3] ? 3 : bk[3], bi[4] ? 4 : bk[4],  bi[5] ? 5 : bk[5],
+                 bi[6] ? 6 : bk[6], bi[7] ? 7 : bk[7],  bi[8] ? 8 : bk[8],
+                 bi[9] ? 9 : bk[9], bi[0] ? 10 : bk[0], bi[1] ? 1 : bk[1],
+                 bi[2] ? 2 : bk[2], bi[3] ? 3 : bk[3],  bi[4] ? 4 : bk[4],
+                 bi[5] ? 5 : bk[5], bi[6] ? 6 : bk[6],  bi[7] ? 7 : bk[7],
+                 bi[8] ? 8 : bk[8], bi[9] ? 9 : bk[9],  bi[0] ? 20 : bk[0],
+                 bi[1] ? 1 : bk[1], bi[2] ? 2 : bk[2],  bi[3] ? 3 : bk[3],
+                 bi[4] ? bj[4] : 4, bi[5] ?: 5,         bi[6] ?: 6,
+                 bi[7] ? 0 : 7,     bi[8] ?: 8,         bi[9] ? 0 : 9,
+                 bi[0] ? 0 : 30,    bi[1] ?: 1}),
+          (d __attribute__((vector_size(2 * sizeof(d)))))
+                  __builtin_shufflevector(
+                      __builtin_convertvector(
+                          __builtin_shufflevector(bb, bb, 2, 7, 21, 6),
+                          e __attribute__((vector_size(4 * sizeof(e))))),
+                      __builtin_convertvector(
+                          (c __attribute__((vector_size(4)))){aw, aw},
+                          e __attribute__((vector_size(4 * sizeof(e))))),
+                      5, 1) +
+              (__builtin_convertvector(
+                   __builtin_shufflevector(bb, bb, 4, 5),
+                   e __attribute__((vector_size(2 * sizeof(e))))) <=
+               __builtin_convertvector(
+                   (c __attribute__((vector_size(2)))){aw},
+                   e __attribute__((vector_size(2 * sizeof(e)))))),
+          n ? bb[5] << n : aw),
+       g __attribute__((vector_size(16 * sizeof(g)))));
+   ag(aw & t);
+   at = aj(aw, v[1]);
+   au = ah(at, aw);
+   ba = af((1 == ax != aw) <= aw <= au, aw);
+   ao(0, &bd[0], &r);
+   o = ay;
+   an(aq, aw, k);
+   av = am(ar, l, k);
+   *be = ai(*be);
+   al(x, as, &bd[0], aw);
+   bg = ak(u, &s, &bf, aw, aw);
+   as = *aa;
+   return m;
+ }
diff -Nrcpad gcc-15-20251101/gcc/testsuite/gcc.target/riscv/rvv/base/pr122270-1.c gcc-15-20251108/gcc/testsuite/gcc.target/riscv/rvv/base/pr122270-1.c
*** gcc-15-20251101/gcc/testsuite/gcc.target/riscv/rvv/base/pr122270-1.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20251108/gcc/testsuite/gcc.target/riscv/rvv/base/pr122270-1.c	Sat Nov  8 22:32:59 2025
***************
*** 0 ****
--- 1,10 ----
+ /* { dg-options "" } */
+ /* { dg-do compile } */
+ /* { dg-add-options riscv_v } */
+ /* PR target/122270 */
+ 
+ #include "riscv_vector.h"
+ 
+ void a(vfloat32m1_t b, vfloat32m1x4_t *c) {
+   *c = __riscv_vset_v_f32m1_f32m1x4(*c, 3, b);
+ }
